ADF4356 datasheet(13/35 Pages) AD

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Data Sheet

ADF4356

Rev. 0 | Page 13 of 35

The FRAC2 and MOD2 fraction results in outputs with zero

frequency error for channel spacings when

fPFD/GCD(fPFD/fCHSP) < 268,435,455

(6)

where:

fPFD is the frequency of the phase frequency detector.

GCD is a greatest common denominator function.

fCHSP is the desired channel spacing frequency.

If zero frequency error is not required, the MOD1 and MOD2

denominators operate together to create a 52-bit resolution

modulus.

INT N Mode

When FRAC1 and FRAC2 are 0, the synthesizer operates in

integer-N mode.

R Counter

The 10-bit R counter allows the input reference frequency

(REFIN) to be divided down to produce the reference clock to

the PFD. Division ratios from 1 to 1023 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND

CHARGE PUMP

The PFD takes inputs from the R counter and N counter and

produces an output proportional to the phase and frequency

difference between them. Figure 22 is a simplified schematic of

the phase frequency detector. The PFD includes a fixed delay

element that sets the width of the antibacklash pulse. This pulse

ensures that there is no dead zone in the PFD transfer function

and provides a consistent reference spur level. Set the phase

detector polarity to positive on this device because of the

positive tuning of the VCO.

CLR2

DOWN

HIGH

–IN

+IN

CHARGE

PUMP

DELAY

CLR1

Figure 22. PFD Simplified Schematic

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4356 allows the user to access

various internal points on the chip. The M3, M2, and M1 bits in

MUXOUT section in block diagram form.

SDGND

DVDD

CONTROL

MUX

MUXOUT

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R DIVIDER OUTPUT

N DIVIDER OUTPUT

SDGND

RESERVED

THREE-STATE OUTPUT

DVDD

Figure 23. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4356 digital section includes a 10-bit R counter, a

16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 28-bit

auxiliary fractional counter, and a 28-bit auxiliary modulus

counter. Data clocks into the 32-bit shift register on each rising

edge of CLK. The data clocks in MSB first. Data transfers from

the shift register to one of 13 latches on the rising edge of LE.

The state of the four control bits (C4, C3, C2, and C1) in the

shift register determines the destination latch. As shown in

Figure 2, the four least significant bits (LSBs) are DB3, DB2,

DB1, and DB0. The truth table for these bits is shown in Table 6.

Figure 26 and Figure 27 summarize the programming of the

latches.

Table 6. Truth Table for the C4, C3, C2, and C1 Control Bits

Control Bits

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