Data Sheet

ADF4356

Rev. 0 | Page 21 of 35

RD2

REFERENCE

DOUBLER

0

DISABLED

1

ENABLED

RD1

REFERENCE DIVIDE BY 2

0

DISABLED

1

ENABLED

CP4

CP3

CP2

CP1

ICP (mA)

5.1k

Ω

0

0

0

0

0.30

0

0

0

1

0.60

0

0

1

0

0.90

0

0

1

1

1.20

0

1

0

0

1.50

0

1

0

1

1.80

0

1

1

0

2.10

0

1

1

1

2.40

1

0

0

0

2.70

1

0

0

1

3.00

1

0

1

0

3.30

1

0

1

1

3.60

1

1

0

0

3.9

.90

1

1

0

1

4.20

1

1

1

0

4.50

1

1

1

1

4..80

R10

R9

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

R2

R1

R DIVIDER (R)

0

0

0

1

1

0

0

1

0

2

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1

1

0

0

1020

1

1

0

1

1021

1

1

1

0

1022

1

1

1

1

1023

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5

DB4

DB3

DB2

DB1

0

0

M3

M2

M1

RD2

RD1

R10

R9

R8

R7

R6

R5

R4

R3

R2

R1

D1

CP4

CP3

CP2

CP1

U6

U5

U4

U3

U2

U1

C3(1) C2(0)

C1(0)

CURRENT

SETTING

10-BIT R COUNTER

CONTROL

BITS

MUXOUT

U5

LDP

0

1.8V

1

3.3V

U4

PD POLARITY

0

NEGATIVE

1

POSITIVE

U3

POWER DOWN

0

DISABLED

1

ENABLED

U2

CP

THREE-STATE

0

DISABLED

1

ENABLED

U1

COUNTER

RESET

0

DISABLED

1

ENABLED

D1

DOUBLE BUFFERED

REGISTER 6, BITS[DB23:DB21]

0

DISABLED

1

ENABLED

U6

REFIN

0

SINGLE

1

DIFF

M3

M2

M1

OUTPUT

0

0

0

THREE-STATE OUTPUT

0

0

1

DVDD

0

1

0

SDGND

0

1

1

R DIVIDER OUTPUT

1

0

0

N DIVIDER OUTPUT

1

0

1

ANALOG LOCK DETECT

1

1

0

DIGITAL LOCK DETECT

1

1

1

RESERVED

DB0

C4(0)

RESERVED

DBR

DBR

Figure 32. Register 4

REGISTER 4

Control Bits

With Bits[C4:C1] set to 0100, Register 4 is programmed. Figure 32

shows the input data format for programming this register.

Reserved

Bits[DB31:DB30] are reserved and must be set to 0.

MUXOUT

The on-chip multiplexer (MUXOUT) is controlled by

Bits[DB29:DB27]. For additional details, see Figure 32.

When changing frequency, that is, writing Register 0, MUXOUT

must not be set to N divider output or R divider output. If needed,

enable these functions after locking to the new frequency.

Reference Doubler

Setting the RD2 bit (Bit DB26) to 0 feeds the reference frequency

signal directly to the 10-bit R counter, disabling the doubler.

Setting this bit to 1 multiplies the reference frequency by a factor

of 2 before feeding it into the 10-bit R counter. When the doubler

input to the fractional synthesizer. When the doubler is enabled,

both the rising and falling edges of the reference frequency become

active edges at the PFD input.

The maximum allowable reference frequency when the doubler

is enabled is 80 MHz.

RDIV2

Setting the RDIV2 bit (Bit DB25) to 1 inserts a divide by 2,

toggle flip-flop between the R counter and PFD, which extends

the maximum reference frequency input rate. This function

provides a 50% duty cycle signal at the PFD input.

10-Bit R Counter

The 10-bit R counter divides the input reference frequency

ratios range from 1 to 1023.

Double Buffer

The D1 bit (Bit DB14) enables or disables double buffering of

the RF divider select bits (Bits[DB23:DB21]) in Register 6. The

Program Modes section explains how double buffering works.

Charge Pump Current Setting

The CP4 to CP1 bits (Bits[DB13:DB10]) set the charge pump

current. Set this value to the charge pump current that the loop

filter is designed with (see Figure 32). For the lowest spurs, the

0.9 mA setting is recommended.