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FDC37B779 Datasheet(PDF) 88 Page - SMSC Corporation

Part # FDC37B779
Description  ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES
PDF  196 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

FDC37B779 Datasheet(HTML) 88 Page - SMSC Corporation

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latches the data from the SData bus for the
PData bus.
7.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
EPP 1.7 Read
The timing for a read operation (data) is shown
in timing diagram EPP 1.7 Read Data cycle.
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle
can complete when nWAIT is inactive high.
Read Sequence of Operation
1.
The host sets PDIR bit in the control
register to a logic "1".
This deasserts
nWRITE and tri-states the PData bus.
2.
The host selects an EPP register and drives
nIOR active.
3.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
4.
If
nWAIT
is
asserted,
IOCHRDY
is
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
5.
The Peripheral drives PData bus valid.
6.
The Peripheral deasserts nWAIT, indicating
that PData is valid and the chip may begin
the termination phase of the cycle.
7.
When the host deasserts nIOR the chip
deasserts nDATASTB or nADDRSTRB.
8.
Peripheral tri-states the PData bus.
9.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.



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