Si4021

21

11. Status Register Read Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

- -

With this command, it is possible to read the chip’s status register through the nIRQ pin. This command clears the last serviced interrupt and

processing the next pending one will start (if there is any).

Status Register Read Sequence

nSEL

SCK

SDI

nIRQ

0

instruction

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

POR

PB1

PB2

PB3

PB4

LBD

WK-UP

nIRQ

status out

12. PLL Setting and Reset Mode Command

bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

POR

1

1

0

1

0

0

1

0

bw1

bw0

0

0

0

0

dr

0

D200h

Bits 7-6 <bw1 : bw0> select the PLL bandwidth:

bw1 bw0

Max datarate

[kbps]

Phase Noise at 1MHz offset

[dBc/Hz] (typical)

Charge pump current

0

1

19.2

-112

25%

1

1

38.4

-110

33%

0

0

68.9

-107

50%

1

0

115.2

-102

100%

Bit 1 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 600 mV glitch in the power supply may cause a system reset. For

more detailed description see the Reset modes section.