2.4 R1 REGISTER

This register is used to configure the N divider for the IF synthesizer. A single word write to this register is all that is required to

power up and tune the synthesizer to the desired frequency.

Reg

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9876543210

DATA[20:0]

C2

C1

C0

R1

IF_

PD

0

0

0

IF_N[16:0]

0

0

1

2.4.1 IF_N[16:0] — N Divider Ratio,IF Synthesizer

The IF_N[16:0] word is used to setup up the N Divider Ratio for the IF synthesizer. The IF N counter is actually a combination of

an IF A counter, IF B counter, and an IF 8/9 prescaler. The relationship between IF_N, IF_B, and IF_A is shown below.

IF_N=8x IF_B + IF_A

Although the IF_N counter value can created by programming the IF_B and IF_A values, it is easier to simply convert the IF N

counter value into binary and program the entire IF_N[16:0] word in this manner. The fact that the IF N counter has a prescaler

is what puts restrictions on IF_N values less than 56.

IF_N[16:0]

IF_B[13:0]

IF_A[2:0]

16

15

14

13

12

11

10

9876543

2

1

0

0-23

Divide ratios of less than 24 are not allowed.

24-55

Legal divide ratios in this range are: 24-27, 32-36, 40-45, and 48-54.

56

00000

0

0

0000111

0

0

0

57

00000

0

0

0000111

0

0

1

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

...

131071

11111

1

1

1111111

1

1

1

2.4.2 IF_PD — Power Down, IF Synthesizer

Activation of the IF Synthesizer power down bit results in the disabling of the respective N divider and de-biasing of its respective

Fin inputs (to a high impedance state). The respective R divider functionality also becomes disabled when the power down bit is

activated. The OSCinIF pin reverts to a high impedance state when both RF and IF power down bits are asserted. Power down

forces the respective charge pump and phase comparator logic to a TRI-STATE condition. The MICROWIRE control register

remains active and capable of loading and latching in data during all of the power down modes.

Both synchronous and asynchronous power down modes are supported. The power down mode bit R6[8] is used to select

between synchronous and asynchronous power down. The MICROWIRE control register remains active and capable of loading

and latching in data in either power down mode.

Synchronous Power Down Mode: The IF synthesizer can be synchronously powered down by first setting the power down

mode bit HIGH (R6[8] = 1) and then asserting its power down bit (R1[23] = 1). The power down function is gated by the charge

pump. Once the power down bit is loaded, the part will go into power down mode upon the completion of a charge pump pulse

event.

Asynchronous Power Down Mode: The IF synthesizer can be asynchronously powered down by first setting the power down

mode bit LOW (R6[8] = 0) and then asserting its power down bit (R1[23]] = 1). The power down function is NOT gated by the

charge pump. Once the power down bit is loaded, the part will go into power down mode immediately

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