ADS5270

SBAS293D − JANUARY 2004 − REVISED MAY 2004

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6

SERIAL INTERFACE TIMING

ADDRESS

DATA

DESCRIPTION

REMARKS

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0. LVDS BUFFERS

0

0

Normal ADC Output

0

1

Deskew Pattern

Patterns Get Reversed in MSB First

Mode of LVDS

1

0

Sync Pattern

Patterns Get Reversed in MSB First

Mode of LVDS

1

1

Custom Pattern

Mode of LVDS

0

0

Output Current in LVDS = 3.5mA

0

1

Output Current in LVDS = 2.5mA

1

0

Output Current in LVDS = 4.5mA

1

1

Output Current in LVDS = 6.0mA

0

0

0

1

1. LSB/MSB MODE

D3

D2

D1

D0

Default LVDS Clock Output Current

0

X

X

1

2X LVDS Clock Output Current

0

0

X

X

LSB Mode

0

1

X

X

MSB Mode

0

0

1

0

2. POWER-DOWN ADC CHANNELS

D3

D2

D1

D0

X

X

X

X

Power-Down Channels 1 to 4; D3 is

for Channel 4 and D0 for Channel 1

Example: 1010 Powers Down

Channels 4 and 2 and Keeps

Channels 1 and 3 Alive

0

0

1

1

3. POWER-DOWN ADC CHANNELS

D3

D2

D1

D0

X

X

X

X

Power-Down Channels 5 to 8; D3 is

for Channel 8 and D0 for Channel 5

CUSTOM PATTERN (registers 4-6)

D3

D2

D1

D0

0

1

0

0

MSB

X

X

X

0

1

0

1

X

X

X

X

Bits for Custom Pattern

0

1

1

0

X

X

X

LSB

TEST PATTERNS(1)

Deskew

101010101010

Sync

000000111111

Custom

Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following order:

D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6)

where, for example, D0(4) refers to the D0 bit of register 4, etc.

(1) Default is LSB first. If MSB is selected the above patterns will be reversed.