14

ICS950810

0472F—01/12/04

All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there

is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the

standard skew described below as Tpci.

3V66 & PCI Phase Relationship

3V66 (1:0)

3V66 (4:2)

3V66_5

PCICLK_F (2:0) PCICLK (6:0)

Tpci

Skews at Common Transition Edges

GROUP

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

PCI

1

127

500

ps

3V66

1

67

250

ps

3V66 to PCI

3V66 (5:0) leads 33MHz PCI

1.5

3.5

ns