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ICS950810 Datasheet(PDF) 11 Page - Integrated Circuit Systems

Part # ICS950810
Description  Frequency Generator with 200MHz Differential CPU Clocks
PDF  19 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS950810 Datasheet(HTML) 11 Page - Integrated Circuit Systems

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11
ICS950810
0472F—01/12/04
I2C Tables
Pin #
Name
0
1
PWD
Bit 7
-
Spread Enabled
Spread Spectrum Control
RW
OFF
ON
0
Bit 6
-
CPU_T(2:0)
Power down mode output
level
0= CPU driven in power
down
1= undriven
RW
HIGH
LOW
0
Bit 5
35
3V66_1/VCH_CLK
VCH/66.66 Select
RW
66.66
48.00
0
Bit 4
53
CPU_STOP#*
Reflects value of pin
R
Stop
Active
X
Bit 3
34
PCI_STOP#*
Reflects value of pin at
power up. Also can be set.
R/RW
Stop
Active
1
Bit 2
40
FS2
Frequency Selection
RW
-
-
X
Bit 1
55
FS1
Frequency Selection
RW
-
-
X
Bit 0
54
FS0
Frequency Selection
RW
-
-
X
Control Function
Affected Pin
BYTE
0Type
Bit Control
Pin #
Name
0
1
PWD
Bit 7
43
MULTSEL0*
Reflects value of pin
R
-
-
x
Bit 6
-
CPU_T(2:0)
CPU_Stop mode output level
0= CPU driven when stopped
1 = undriven
RW
HIGH
LOW
0
Bit 5
45, 44
CPUCLKT2
CPUCLKC2
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
Freerun
0
Bit 4
49, 48
CPUCLKT1
CPUCLKC1
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
Freerun
0
Bit 3
52, 51
CPUCLKT0
CPUCLKC0
Allow control of output with
assertion of CPU_STOP#.
RW
Not
Freerun
Freerun
0
Bit 2
45, 44
CPUCLKT2
CPUCLKC2
Output control
RW
Disable Enable
1
Bit 1
49, 48
CPUCLKT1
CPUCLKC1
Output control
RW
Disable Enable
1
Bit 0
52, 51
CPUCLKT2
CPUCLKC2
Output control
RW
Disable Enable
1
BYTE
1
Control Function
Affected Pin
Type
Bit Control



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