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ICS950810

0472F—01/12/04

CPU_STOP# - Assertion (transition from logic "1" to logic "0")

Assertion of CPU_STOP# Waveforms

CPU_STOP# Functionality

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The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I

assertion of CPU_STOP# are to be stopped after their next transition. When the I

the final state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive

current values. The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not

be driven . When the I

and CPU# outputs will not be driven.

CPU_STOP#

CPUT

CPUC

CPU_STOP# - De-assertion (transition from logic "0" to logic "1")

De-assertion of CPU_STOP# Waveforms

All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the

de-assertion to active outputs is to be defined to be tetween 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit

6 of Byte 1 is programmed to "1" then the stopped CPU outputs will be driven High within 3 nS of CPU_Stop# de-assertion.