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AD9364BBCZ Datasheet(PDF) 7 Page - Analog Devices

Part # AD9364BBCZ
Description  Point to point communication systems
PDF  33 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9364BBCZ Datasheet(HTML) 7 Page - Analog Devices

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AD9364
Data Sheet
Parameter1
Symbol Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 1.8 V
DATA_CLK Clock Period
tCP
16.276
ns
61.44 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
ns
Tx Data
TX_FRAME, P0_D, and P1_D
Setup to FB_CLK
tSTX
1
ns
Hold to FB_CLK
tHTX
0
ns
DATA_CLK to Data Bus Output
Delay
tDDRX
0
1.5
ns
DATA_CLK to RX_FRAME
Delay
tDDDV
0
1.0
ns
Pulse Width
ENABLE
tENPW
tCP
ns
TXNRX
tTXNRXPW
tCP
ns
FDD independent ENSM
mode
TXNRX Setup to ENABLE
tTXNRXSU
0
ns
TDD ENSM mode
Bus Turnaround Time
Before Rx
tRPRE
2 × tCP
ns
TDD mode
After Rx
tRPST
2 × tCP
ns
TDD mode
Capacitive Load
3
pF
Capacitive Input
3
pF
DIGITAL DATA TIMING (CMOS),
VDD_INTERFACE = 2.5 V
DATA_CLK Clock Period
tCP
16.276
ns
61.44 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
ns
Tx Data
TX_FRAME, P0_D, and P1_D
Setup to FB_CLK
tSTX
1
ns
Hold to FB_CLK
tHTX
0
ns
DATA_CLK to Data Bus Output
Delay
tDDRX
0
1.2
ns
DATA_CLK to RX_FRAME
Delay
tDDDV
0
1.0
ns
Pulse Width
ENABLE
tENPW
tCP
ns
TXNRX
tTXNRXPW
tCP
ns
FDD independent ENSM
mode
TXNRX Setup to ENABLE
tTXNRXSU
0
ns
TDD ENSM mode
Bus Turnaround Time
Before Rx
tRPRE
2 × tCP
ns
TDD mode
After Rx
tRPST
2 × tCP
ns
TDD mode
Capacitive Load
3
pF
Capacitive Input
3
pF
DIGITAL DATA TIMING (LVDS)
DATA_CLK Clock Period
tCP
4.069
ns
245.76 MHz
DATA_CLK and FB_CLK Pulse
Width
tMP
45% of tCP
55% of tCP
ns
Tx Data
TX_FRAME and TX_D
Setup to FB_CLK
tSTX
1
ns
Hold to FB_CLK
tHTX
0
ns
DATA_CLK to Data Bus Output
Delay
tDDRX
0.25
1.25
ns
DATA_CLK to RX_FRAME
Delay
tDDDV
0.25
1.25
ns
Pulse Width
ENABLE
tENPW
tCP
ns
TXNRX
tTXNRXPW
tCP
ns
FDD independent ENSM
mode
TXNRX Setup to ENABLE
tTXNRXSU
0
ns
TDD ENSM mode
Rev. C | Page 6 of 32



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