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AD9364

Data Sheet

Pin No.

Type1

Mnemonic

Description

J12

I/O

P1_D1/RX_D0_P

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D1, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D0_P) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

K1, L1

RXC_P, RXC_N

Receive Channel Differential Input C. Alternatively, each pin can be used as a

single-ended input. These inputs experience degraded performance above

3 GHz. Unused pins must be tied to ground.

VDDA1P3_TX_SYNTH

1.3 V Supply Input.

VDDA1P3_BB

1.3 V Supply Input.

RESETB

Asynchronous Reset. Logic low resets the device.

SPI_ENB

SPI Enable Input. Set this pin to logic low to enable the SPI bus.

I/O

P1_D8/RX_D4_N

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D8, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D4_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

I/O

P1_D6/RX_D3_N

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D6, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D3_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

I/O

P1_D4/RX_D2_N

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D4, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D2_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

K10

I/O

P1_D2/RX_D1_N

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D2, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 1. Alternatively, this pin (RX_D1_N) can function as part of the LVDS

6-bit Rx differential output bus with internal LVDS termination.

K11

I/O

P1_D0/RX_D0_N

Digital Data Port P1/Receive Differential Output Bus. This is a dual function pin.

As P1_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 1. Alternatively, this pin (RX_D0_N) can function as part of the LVDS 6-bit Rx

differential output bus with internal LVDS termination.

RBIAS

Bias Input Reference. Connect this pin through a 14.3 kΩ (1% tolerance) resistor

to ground.

AUXADC

Auxiliary ADC Input. If this pin is unused, tie it to ground.

SPI_DO

SPI Serial Data Output in 4-Wire Mode, High-Z in 3-Wire Mode.

M1, M2

RXA_P, RXA_N

Receive Channel Differential Input A. Alternatively, each pin can be used as a

single-ended input. Unused pins must be tied to ground.

TX_MON

Transmit Channel Power Monitor Input. If this pin is unused, tie it to ground.

M7, M8

TXA_P, TXA_N

Transmit Channel Differential Output A. Unused pins must be tied to 1.3 V.

M9, M10

TXB_P, TXB_N

Transmit Channel Differential Output B. Unused pins must be tied to 1.3 V.

M11, M12

XTALP, XTALN

Reference Frequency Crystal Connections. When a crystal is used, connect it

between these two pins. When an external clock source is used, connect it to

XTALN and leave XTALP unconnected.

I is input, O is output, I/O is input/output, NC is not connected.

Rev. C | Page 14 of 32

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