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AD9364BBCZ Datasheet(PDF) 12 Page - Analog Devices |
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AD9364BBCZ Datasheet(HTML) 12 Page - Analog Devices |
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12 / 33 page  Data Sheet AD9364 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration, Top View Table 13. Pin Function Descriptions Pin No. Type1 Mnemonic Description A1, A2, A4 to A6, B1, B2, B12, C1, C2, C7 to C12, D1, E1, F1, F3, H2, H3, H6, J2, K2, L2, L3, L7 to L12, M4, M6 I VSSA Analog Ground. Tie these pins directly to the VSSD digital ground on the printed circuit board (one ground plane). A3, M3 NC NC No Connect. Do not connect to these pins. A7 to A10, D3 I VDDA1P3_RX_TX 1.3 V Supply Input. A11 I VDDA1P1_TX_VCO Transmit VCO Supply Input. Connect to B11. A12 I TX_EXT_LO_IN External Transmit Local Oscillator (LO) Input. When this pin is unused, tie it to ground. B3 O AUXDAC1 Auxiliary DAC 1 Output. B4 to B7 O GPO_3 to GPO_0 3.3 V Capable General-Purpose Outputs. B8 I VDD_GPO 2.5 V to 3.3 V Supply for the Auxiliary DAC and General-Purpose Output Pins. When the VDD_GPO supply is not used, this supply must be set to 1.3 V. B9 I VDDA1P3_TX_LO Transmit LO 1.3 V Supply Input. B10 I VDDA1P3_TX_VCO_LDO Transmit VCO LDO 1.3 V Supply Input. Connect to B9. B11 O TX_VCO_LDO_OUT Transmit VCO LDO Output. Connect B11 to A11 and a 1 μF bypass capacitor in series with a 1 Ω resistor to ground. C3 O AUXDAC2 Auxiliary DAC 2 Output. C4 I TEST/ENABLE Test Input. Ground this pin for normal operation. ANALOG I/O DC POWER DIGITAL I/O GROUND NO CONNECT 1 2 3 4 5 6 7 8 9 10 11 12 K A B C D E F G H J L M VSSA VSSA NC VSSA VSSA VSSA VDDA1P3_ RX_TX VDDA1P3_ RX_TX VDDA1P3_ RX_TX VDDA1P3_ RX_TX VDDA1P1_ TX_VCO TX_EXT_ LO_IN VSSA VSSA AUXDAC1 GPO_3 GPO_2 GPO_1 GPO_0 VDD_GPO VDDA1P3_ TX_LO VDDA1P3_ TX_VCO_ LDO TX_VCO_ LDO_OUT VSSA VSSA VSSA AUXDAC2 TEST/ ENABLE CTRL_IN0 CTRL_IN1 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P3_ RX_RF VDDA1P3_ RX_TX CTRL_OUT0 CTRL_IN3 CTRL_IN2 P0_D9/ TX_D4_P P0_D7/ TX_D3_P P0_D5/ TX_D2_P P0_D3/ TX_D1_P P0_D1/ TX_D0_P VSSD VSSA VDDA1P3_ RX_LO VDDA1P3_ TX_LO_ BUFFER CTRL_OUT1 CTRL_OUT2 CTRL_OUT3 P0_D11/ TX_D5_P P0_D8/ TX_D4_N P0_D6/ TX_D3_N P0_D4/ TX_D2_N P0_D2/ TX_D1_N P0_D0/ TX_D0_N VSSA VDDA1P3_ RX_VCO_ LDO VSSA CTRL_OUT6 CTRL_OUT5 CTRL_OUT4 VSSD P0_D10/ TX_D5_N VSSD FB_CLK_P VSSD VDDD1P3_ DIG RX_EXT_ LO_IN RX_VCO_ LDO_OUT VDDA1P1_ RX_VCO CTRL_OUT7 EN_AGC ENABLE RX_ FRAME_N RX_ FRAME_P TX_ FRAME_P FB_CLK_N DATA_ CLK_P VSSD RXB_P VSSA VSSA TXNRX SYNC_IN VSSA VSSD P1_D11/ RX_D5_P TX_ FRAME_N VSSD DATA_ CLK_N VDD_ INTERFACE RXB_N VSSA VDDA1P3_ RX_SYNTH SPI_DI SPI_CLK CLK_OUT P1_D10/ RX_D5_N P1_D9/ RX_D4_P P1_D7/ RX_D3_P P1_D5/ RX_D2_P P1_D3/ RX_D1_P P1_D1/ RX_D0_P RXC_P VSSA VDDA1P3_ TX_SYNTH VDDA1P3_ BB RESETB SPI_ENB P1_D8/ RX_D4_N P1_D6/ RX_D3_N P1_D4/ RX_D2_N P1_D2/ RX_D1_N P1_D0/ RX_D0_N VSSD RXC_N VSSA VSSA RBIAS AUXADC SPI_DO VSSA VSSA VSSA VSSA VSSA VSSA RXA_P RXA_N NC VSSA TX_MON VSSA TXA_P TXA_N TXB_P TXB_N XTALP XTALN Rev. C | Page 11 of 32 |
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