ADE9078ACPZ datasheet(55/108 Pages) AD

55 / 108 page

ADE9078

Data Sheet

Rev. 0 | Page 54 of 107

Similarly, VPEAK stores the peak voltage value in VPEAKVAL,

Bits[23:0]. VPEAKVAL is equal to xV_PCF/25.

VPPHASE, Bit 2 indicates that Phase C had the peak voltage

value; VPPHASE, Bit 1 indicates Phase B; and VPPHASE, Bit 0

indicates Phase A.

When the user reads the IPEAK register, its value is reset. The

same is true for reading VPEAK.

MEASUREMENTS (PSM2)

Overview

It is possible to tamper with an energy meter by disconnecting

the voltage inputs or the neutral. Some regions require monitoring

of the current inputs for several days after the voltage inputs to

the meter have been cut, to check for this kind of tamper condition.

The PSM1 and PSM2 operating modes in conjunction with

PSM3 enable low power consumption when checking for and

billing for a tamper of this kind.

To use this feature, first write the PSM2_CFG register to

configure the current threshold to compare the input current

level to and for how long to perform the detection while in

either PSM0 or PSM1 operating modes. Then, change the PM1

and PM0 pins to 1 and 0, respectively, to select the PSM2

operating mode. To achieve the specified accuracy, stay in

PSM2 mode for the time indicated in Table 8 before checking

the IRQ0 and IRQ1 pins to see if a tamper has occurred.

If no tampering is detected, change the PM1 and PM0 pins to 1

and 1, respectively, to enter PSM3 for one minute. Then, enter

PSM2 by making PM1 and PM0 pins to 1 and 0, respectively, to

check for tamper and begin the process again.

Low Power Comparator

In the PSM2 operating mode, the ADE9078 enters a low power

state where only a low power comparator is active. The 1.8 V

LDOs, ADCs, DSP, and crystal oscillator are turned off.

In this mode, the input currents (IA, IB, IC) are compared

against a user selected level set in PSM2_CFG register.

The IRQ0 and IRQ1 pins indicate whether any of the three

currents exceeds the threshold. The amount of time allowed for the

detection is decided by the user and set in the LPLINE bits of

the PSM2_CFG register. The measurement time is the period of

(LPLINE + 4)/50 sec. The ADE9078 indicates that a tamper is

detected if at least LPLINE + 1 peaks are obtained on a current

channel. The maximum allowed value in LPLINE is 0x0A.

For example, if LPLINE = 2, six cycles of measurement time and

three peaks are required on a given channel to indicate a tamper

event.

The level to compare the current against is set in the

PSM2_CFG register, PKDET_LVL bits, as shown in Table 22.

Table 22. PSM2 Current Peak Detect Thresholds

PKDET_LVL

Threshold Level

144:1

271:1

377:1

498:1

578:1

660:1

764:1

845:1

970:1

1100:1

1196:1

1312:1

1371:1

1464:1

1559:1

1629:1

After the configured measurement time set and (LPLINE +

4)/50 sec has elapsed, the IRQ0 and IRQ1 pins indicate if a

tamper has occurred. If IRQ0 is low, all the currents have had

less than LPLINE + 1 peaks; no tamper is detected. If IRQ1 is

low, at least one current was above LPLINE + 1 peaks and a

tamper is detected.

After the tamper is detected, switch to PSM1 power mode by

changing the PM1 and PM0 pins to 0 and 1, respectively, to

measure key measurements quickly: IRMS, VRMS, active

power, VAR, VA, and others (see the Measurements (PSM1)

section for more information).

ADE9078ACPZ Datasheet(PDF) 55 Page - Analog Devices

ADE9078ACPZ Datasheet(HTML) 55 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL