ADE9078ACPZ datasheet(91/108 Pages) AD

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ADE9078

Data Sheet

Rev. 0 | Page 90 of 107

Addr. Name

Bits

Bit Name

Settings Description

Reset

Access

0x401 VPEAK

[31:27] RESERVED

Reserved.

0x0

[26:24] VPPHASE

These bits indicate which phases generate

VPEAKVAL value. Note that the PEAKSEL[2:0] bits

in the CONFIG3 register determine which voltage

channels to monitor the peak value on. When

VPPHASE[0] is 1, Phase A voltage generated

VPEAKVAL[23:0] value. Similarly, VPPHASE[1]

indicates Phase B and VPPHASE[2] indicates Phase

C voltage generated the peak value.

0x0

[23:0]

VPEAKVAL

The VPEAK register stores the absolute value of the

peak voltage. VPEAK is equal to xV_PCF/25.

0x0

0x402 STATUS0

[31:25] RESERVED

Reserved.

0x0

MISMTCH

This bit is set to indicate a change in the

relationship between ISUMRMS and ISUMLVL.

0x0

R/W1

COH_WFB_FULL

This bit is set when the waveform buffer is full with

resampled data, which is selected when

WF_CAP_SEL = 0 in the WFB_CFG register.

0x0

R/W1

WFB_TRIG

This bit is set when one of the events configured in

WFB_TRIG_CFG occurs.

0x0

R/W1

PF_RDY

This bit goes high to indicate when the power

factor measurements have been updated, every

1.024 sec.

0x0

R/W1

[20:19] RESERVED

Reserved.

0x0

PWRRDY

This bit is set when the power values in the

xWATT_ACC, xVA_ACC, xVAR_ACC, xFVAR_ACC

registers have been updated, after PWR_TIME

4 kSPS samples.

0x0

R/W1

PAGE_FULL

This bit is set when a page enabled in the

WFB_PG_IRQEN register has been filled with fixed

data rate samples, when WF_CAP_SEL bit in the

WFB_CFG register = 0.

0x0

R/W1

WFB_TRIG_IRQ

This bit is set when the waveform buffer has

stopped filling after an event configured in

WFB_TRIG_CFG occurs. This happens with fixed

data rate samples only, when WF_CAP_SEL bit in

the WFB_CFG register = 0.

0x0

R/W1

DREADY

This bit is set when new waveform samples are

ready. The update rate depends on the data

selected in the WF_SRC bits in the WFB_CFG

0x0

R/W1

CF4

This bit is set when a CF4 pulse is issued, when the

CF4 pin goes from a high to low state.

0x0

R/W1

CF3

This bit is set when a CF3 pulse is issued, when the

CF3 pin goes from a high to low state.

0x0

R/W1

CF2

This bit is set when a CF2 pulse is issued, when the

CF2 pin goes from a high to low state.

0x0

R/W1

CF1

This bit is set when a CF1 pulse is issued, when the

CF1 pin goes from a high to low state.

0x0

R/W1

REVPSUM4

This bit is set to indicate if the CF4 polarity

changed sign. For example, if the last CF4 pulse

was positive reactive energy and the next CF4

pulse is negative reactive energy, the REVPSUM4

bit is set. This bit is updated when a CF4 pulse is

output, when the CF4 pin goes from high to low.

0x0

R/W1

ADE9078ACPZ Datasheet(PDF) 91 Page - Analog Devices

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