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Data Sheet

AD5676

Rev. B | Page 19 of 27

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5676 is an octal 16-bit, serial input, voltage output DAC.

The device operates from supply voltages of 2.7 V to 5.5 V. Data

is written to the AD5676 in a 24-bit word format via a 3-wire

serial interface. The AD5676 incorporates a power-on reset

circuit to ensure that the DAC output powers up to a known

output state. The device also has a software power-down mode that

reduces the typical current consumption to typically 1 µA.

TRANSFER FUNCTION

The gain of the output amplifier can be set to ×1 or ×2 using the

gain select pin (GAIN) on the TSSOP package or the gain bit on

the LFCSP package. When the GAIN pin is tied to GND, all eight

DAC outputs have a span from 0 V to VREF. When the GAIN pin

is tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF.

When using the LFCSP package, the gain bit in the gain setup

bit is 0 by default. When the gain bit is 0 the output span of all

eight DACs is 0 V to VREF. When the gain bit is 1 the output

span of all eight DACs is 0 V to 2 × VREF. The gain bit is ignored

on the TSSOP package.

DAC ARCHITECTURE

The DAC architecture implements a segmented string DAC

with an internal output buffer. Figure 41 shows the internal

block diagram.

INPUT

DAC

RESISTOR

STRING

REF (+)

VREF

GND

REF (–)

VOUTx

GAIN

(GAIN = 1 OR 2)

Figure 41. Single DAC Channel Architecture Block Diagram

Figure 42 shows the simplified segmented resistor string DAC

structure. The code loaded to the DAC register determines the

switch on the string that is connected to the output buffer.

Because each resistance in the string has the same value, R, the

string DAC is guaranteed monotonic.

TO OUTPUT

AMPLIFIER

VREF

Figure 42. Simplified Resistor String Structure

Output Amplifiers

The output buffer amplifier generates rail-to-rail voltages on its

output, which gives an output range of 0 V to VDD. The actual

range depends on the value of VREF, the gain setting, the offset error,

and the gain error.

The output amplifiers can drive a load of 1 kΩ in parallel with

10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾

scale settling time of 5 µs.

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