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AD9528 Datasheet(PDF) 51 Page - Analog Devices |
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AD9528 Datasheet(HTML) 51 Page - Analog Devices |
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51 / 68 page  AD9528 Data Sheet Rev. C | Page 50 of 67 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) 0x0315 Channel Output 7 Channel control, Bits[2:0] Fine analog delay enable Fine analog delay, Bits[3:0] 0x40 0x0316 Output format, Bits[1:0] Coarse digital delay, Bits[5:0] 0x00 0x0317 Divide ratio, Bits[7:0] 0x00 0x0318 Channel Output 8 Channel control, Bits[2:0] Fine analog delay enable Fine analog delay, Bits[3:0] 0x00 0x0319 Output format, Bits[1:0] Coarse digital delay, Bits[5:0] 0x00 0x031A Divide ratio, Bits[7:0] 0x04 0x031B Channel Output 9 Channel control, Bits[2:0] Fine analog delay enable Fine analog delay, Bits[3:0] 0x40 0x031C Output format, Bits[1:0] Coarse digital delay, Bits[5:0] 0x00 0x031D Divide ratio, Bits[7:0] 0x00 0x031E Channel Output 10 Channel control, Bits[2:0] Fine analog delay enable Fine analog delay, Bits[3:0] 0x00 0x031F Output format, Bits[1:0] Coarse digital delay, Bits[5:0] 0x00 0x0320 Divide ratio, Bits[7:0] 0x04 0x0321 Channel Output 11 Channel control, Bits[2:0] Fine analog delay enable Fine analog delay, Bits[3:0] 0x40 0x0322 Output format, Bits[1:0] Coarse digital delay, Bits[5:0] 0x00 0x0323 Divide ratio [7:0] 0x00 0x0324 Channel Output 12 Channel control, Bits[2:0] Fine analog delay enable Fine analog delay, Bits[3:0] 0x20 0x0325 Output format, Bits[1:0] Coarse digital delay, Bits[5:0] 0x00 0x0326 Divide ratio, Bits[7:0] 0x00 0x0327 Channel Output 13 Channel control, Bits[2:0] Fine analog delay enable Fine analog delay, Bits[3:0] 0x20 0x0328 Output format, Bits[1:0] Coarse digital delay, Bits[5:0] 0x00 0x0329 Divide ratio, Bits[7:0] 0x00 Sync Control 0x032A Distribution sync Reserved Sync outputs 0x00 0x032B Ignore sync enable Channel 7 ignore sync Channel 6 ignore sync Channel 5 ignore sync Channel 4 ignore sync Channel 3 ignore sync Channel 2 ignore sync Channel 1 ignore sync Channel 0 ignore sync 0x00 0x032C Reserved PLL2 feedback N2 divider ignore sync Channel 13 ignore sync Channel 12 ignore sync Channel 11 ignore sync Channel 10 ignore sync Channel 9 ignore sync Channel 8 ignore sync 0x00 0x032D SYSREF Bypass resample control Channel 6 bypass SYSREF resample Channel 5 bypass SYSREF resample Channel 4 bypass SYSREF resample Channel 3 bypass SYSREF resample Channel 2 bypass SYSREF resample Channel 1 bypass SYSREF resample Channel 0 bypass SYSREF resample Enable VCXO receiver path to distribution 0x00 0x032E Reserved Channel 13 bypass SYSREF resample Channel 12 bypass SYSREF resample Channel 11 bypass SYSREF resample Channel 10 bypass SYSREF resample Channel 9 bypass SYSREF resample Channel 8 bypass SYSREF resample Channel 7 bypass SYSREF resample 0x00 SYSREF Control 0x0400 SYSREF pattern generator K divider K divider, Bits[7:0] 0x00 0x0401 K divider, Bits[15:8] 0x00 0x0402 SYSREF control SYSREF request method SYSREF pattern generator trigger control, Bits[1:0] SYSREF pattern generator clock source Resample clock source for external SYSREF SYSREF test mode, Bits[1:0] SYSREF reset 0x00 0x0403 SYSREF source, Bits[1:0] SYSREF pattern generator mode, Bits[1:0] N-shot mode, Bits[2:0] SPI SYSREF request 0x00 0x0404 SYSREF_IN receiver control Reserved SYSREF IN receiver power-down Single-ended source negative input (CMOS mode) SYSREF differential receiver enable 0x04 |
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