CN-0385

Circuit Note

Rev. 0 | Page 2 of 13

Figure 1. Isolated Multichannel Data Acquisition Simplified Circuit (All Connections and Decoupling Not Shown)

CIRCUIT DESCRIPTION

The circuit shown in Figure 1 is an isolated multichannel data

acquisition signal chain consisting of a multiplexer, programmable

gain stage, ADC driver, and a fully differential, precision, successive

approximation register (SAR) ADC. The channel switching and

gain switching is synchronized to the conversion period of the

ADC.

The system can monitor up to eight channels using a single ADC,

reducing component count and cost compared to systems with

one ADC per channel. Each channel can be configured with

a different gain, allowing for flexibility of input ranges. It is

manipulated by the complex programmable logic device (CPLD)

which can be configured in the Labview graphical user interface

(GUI). The effective sample rate for each channel is equal to the

sample rate of the ADC divided by the total number of channels

being sampled.

The maximum sample rate of the system is limited by the settling

time of the components (such as the programmable gain amplifier

(PGA) bandwidth and RC filter bandwidth) in the analog front

end and the isolated digital interface clock rate which runs at

75 MHz. Multiplexed signals are discontinuous in nature, resulting

in potentially large voltage steps between sampling intervals.

The components in the signal chain must be given adequate time

to settle to these steps before the ADC performs a conversion.

To maximize the time given for the signal to settle, the multiplexer

channels are switched immediately after the ADC begins a new

conversion.

The board power supply can take a dc input from 5 V to 12 V

at the dc jack or 12 V from the SDP-H1 controller board. The

ADP2441 dc-to-dc converter generates 3.3 V for the digital

interface and the ADuM3470 primary supply input. The

ADP5070, ADP7118, and ADP7182 are used to generate

positive and negative ±15 V supplies. The ADP7118 is used to

generate 5 V, 3.3 V, and 1.8 V for the analog and digital power

supplies. The ADuM141E is selected for isolated high speed SPI

communication. It has 150 Mbps maximum data rate, low

propagation delay, and low dynamic power consumption.

Component Selection

The ADG5207 is a high voltage, latch-up proof, 8-channel

differential multiplexer. The ultralow capacitance and charge

injection of these switches make them ideal solutions for data

acquisition and sample-and-hold applications, where low glitch

and fast settling are required. A switching network at the inputs

of the ADG5207 adds compatibility with both single-ended and

differential input signals. The active channel is selected via the

address pins of the device, which are controlled by the CPLD,

and which can be configured in the GUI.

The AD8251 is a programmable gain instrumentation amplifier

that provides selectable gain settings of 1, 2, 4, and 8. The higher

gain settings boost smaller input signals to the full-scale input

range of the AD4003. Each gain setting has its own suitable

input range, which is shown in Table 1.

Table 1. Input Range for Each of the Four Gain Configurations

Gain

Full-Scale Input Range

0.4

±10.24 V

0.8

±5.12 V

1.6

±2.56 V

3.2

±1.28 V

1-OF-8

DECODER

C0+

C7+

ADG5207

VDD

+15V

–15V

DA

AD8475

ADuM3470

ADP2441

FMC

ADuM141E

–

+

–

+

–IN_0.4

–IN_0.8

VCOM

+IN_0.8

+IN_0.4

1.25kΩ

1.25kΩ

1.25kΩ

1.25kΩ

1kΩ

1kΩ

4.99kΩ

4.99kΩ

OUT+

200Ω

120pF

120pF

200Ω

OUT–

1/2

ADA4807-2

1/2

ADA4807-2

100Ω

100pF

100Ω

100pF

+IN

–IN

AD4003

REF VDD VIO

GND

SCK

SDO

SDI

CNV

SCK

SDO

SDI

CS

CNV

ADP5070

ADP7118

5.5V

+16V

+15V

ADP7118

5V

5.5V

5.5V

ADP7118

1.8V

ADP7118

3.3V

ADP7182

–15V

–16V

AD8251

+

–

+

–

–

+

–IN

+IN

–15V

+15V

LOGIC

+

–

DGND WR A1 A0

OUT

REF

–5V

+5V

+5V

C7–

C0–

DB

100Ω

100pF

100Ω

100pF

2.2µF

5V

2.2µF

5V

ADR4540

TP

NC7

VOUT

NC5

NC1

VIN

NC3

GND

CPLD

SDI

SCK

SDO

CS

10µF

0.1µF

1.8V

3.3V 5.5V

3.3V

12V