ACT8870 datasheet(24/38 Pages) ACTIVE-SEMI

24 / 38 page

ACT8870QJ-T

REV 0 23-DEC-2016

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limit threshold.

This immediately shuts down the

regulator and waits 14ms before restarting.

For LDOs, the overcurrent thresholds are set by each

LDO’s Output Current Limit setting. When the output

current reaches the Current Limit threshold, the LDO

limits the output current.

This reduces the output

voltage, creating an undervoltage condition, causing all

supplies to turn off for 100ms before restarting.

The overcurrent fault limits for each output are

adjustable via I2C. Overcurrent fault reporting can be

masked via I2C, but the overcurrent limits are always

active and will shut down the IC when exceeded.

Thermal Warning and Thermal Shutdown

The ACT8870 monitors its internal die temperature and

reports a warning via IRQ when the temperature rises

above the Thermal Interrupt Threshold of typically 135

deg C. It reports a fault when the temperature rises

above the Thermal Shutdown Temperature of typically

165 deg C. A temperature fault shuts down all outputs

unless the fault is masked. Both the fault and the

warning can be masked via I2C. The temperature

warning and fault flags still provide real-time status even

if the faults are masked. Masking just prevents the faults

from being reported via the IRQ pin.

Pin Descriptions

The ACT8870 input and output pins are configurable via

CMI configurations. The following descriptions are refer

to the most common pin functions. Refer to the CMI

Options section in the back of the datasheet for specific

pin functionality for each CMI.

PWREN

The PWREN pin controls the IC’s SLEEP state. When

I2C bit PWREN_MODE = 0, the PWREN pin moves the

IC between the SLEEP and ACTIVE states.

PWREN must be enabled via the PWRDN_EN I2C bit

after power up. PWREN is ignored if the PWRDN_EN

bit is low. The PWREN polarity is controlled by the

PWREN_POL I2C bit. PWREN is active low when

PWREN_POL is high, and active

high when

PWREN_POL is low. The host processor can read the

PWREN status via I2C in the PWREN_STAT I2C bit.

PWREN is referenced to the VIO_IN pin, and is 5.5V

tolerant meaning that PWREN can go to 5.5V even if

VIO_IN is less than 5.5V. PWREN has a 10us

bidirectional filter to prevent noise from triggering

unwanted operation.

EXT_PG

The EXT_PG pin is a dual purpose input. It functions as

either a power good input from an external supply or a

dynamic scaling control input. Configure EXT_PG as a

power good input by setting I2C bit DVS_EN = 0. When

configured as a power good input, EXT_PG can be

used as an input to the nRESETx pins. EXT_PG polarity

is controlled by the EXT_PG_POL bit. EXT_PG is active

high when EXT_PG_POL = 0 and active low when

EXT_PG_POL = 1.

Configure EXT_PG as a dynamic voltage scaling (DVS)

control input by setting I2C bit DVS_EN = 1. When

EXT_PG is de-asserted, all buck regulators regulate to

their VSET0 voltage. When EXT_PG is asserted, the

buck regulators regulate to their VSET1 voltage. Note

that EXT_PG input is only valid for DVS toggling when

the IC is in the ACTIVE state of operation. I2C bit

EXT_PG_POL has no effect in DVS Mode.

EXT_PG is referenced to the VIO_IN pin, and is 5.5V

tolerant meaning that EXT_PG can go to 5.5V even if

VIO_IN is less than 5.5V. The EXT_PG input has a 10us

bidirectional filter to prevent noise from triggering

unwanted operation.

VIO_IN

VIO_IN is the input bias supply for the IC. Apply an input

voltage between 1.62V and 5.5V. Bypass to AGND with

a high quality, 1uF ceramic capacitor.

MODE

Setting MODE = 0 configures Buck1 as a standard

integrated buck regulator. Setting MODE = 1 configures

Buck1 as an integrated bypass switch. In bypass mode,

the Buck1 P-ch power FET is used to sequence the

3.3V supply to the downstream load. This provides full

sequencing flexibility for 3.3V systems by allowing the

3.3V input to be used as the input supply for the other

regulators but still be sequenced in any order for the

downstream loads. Bypass mode is only valid for a 3.3V

input voltage. The MODE pin must be tied directly to

VIN or AGND. MODE is only sampled when VIN

reaches its UVLO threshold during power. Changing

MODE after power up has no effect on functionality. I2C

bit MODE_STAT shows the status of the MODE pin

when it was read at startup.

GPIO

The GPIO pin can be configured as a digital input or an

open drain output. It has multiple uses, including a

sequencing input, sequencing output, status output, or

control input to toggle a supply’s output voltage. Set I2C

bit GPIO_OUT = 0 to configure GPIO as an input. When

using GPIO as an output, GPIO_OUT = 0 configures it

as an open drain output, and GPIO_OUT = 1 configures

it as a logic low output. When used as either an input

or an output, I2C bit GPIO_STAT always provides the

real-time status of the GPIO pin. GPIO_STAT = 0 when

GPIO pin is a logic 0. GPIO_STAT = 1 when GPIO pin

is a logic 1.

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