ACT8870 datasheet(25/38 Pages) ACTIVE-SEMI

25 / 38 page

ACT8870QJ-T

REV 0 23-DEC-2016

Innovative PowerTM

ActiveSwitcherTM is a trademark of Active-Semi.

IRQ

The IRQ pin is an output that issues an interrupt to the

host CPU/Controller when an ACT8870 fault or warning

condition occurs.

IRQ is triggered by:

1. Die temperature exceeding Thermal Interrupt

Threshold of 135C.

2. Any buck regulator reaching peak current limit,

ILIMSET, for 16 cycles after softstart.

3. Any

LDO

regulator

reaching

current

limit,

LDOx_ILIM, for more than 16us after softstart.

4. BUCK1 PMOS switch exceeding Current Detection

threshold 75% of ILIMSET when system is

configured in bypass mode.

IRQ is masked by the I2C register 0x00h bit2

(IRQ_nMASK) by default to mask all IRQ conditions. To

enable IRQ functionality, set IRQ_nMASK = 1. IRQ is an

active-low open drain 5.5V compatible output.

POK

POK indicates that the voltage on the VIN pin is inside

the POK UV and OV Interrupt Thresholds. If the VIN

voltage is above or below these values, POK pulls low

to interrupt the host CPU/Controller. POK is masked by

the I2C bit POK_nMASK by default. To enable POK

functionality, set I2C bit POK_nMASK = 1. I2C bits

POK_OV and POK_UV provide real-time UV and OV

status, even when POK is masked. The POK UV and

OV threshold are configurable via the I2C bits

POK_UV_SET and POK_OV_SET.

POK is an open drain output and is 5.5V tolerant

meaning that POK can be pulled up to 5.5V even if

VIO_IN is less than 5.5V.

nRESET_AUX1 and nRESET_AUX2

nRESET_AUX1 and nRESET_AUX2 pins can be used

to signal that the IC is in the SLEEP state or that the

input voltage is above or below the UV or OV threshold.

They can also be tied to one or a combination of the

power supply’s internal POK signal. These outputs are

immediately asserted low, but follow a programmed

delay when de-asserted. The nRESET_AUX1 delay

time is controlled by the I2C bits RST_AUX1_DLY[2:0],

which programs the delay between 400us and 2mS in

227us steps. The nRESET_AUX2 delay time is

controlled by the I2C bits RST_AUX2_DLY[2:0], which

programs the delay between 200us and 1ms in 114us

steps. These pins are open drain output and 5.5V

tolerant meaning that they can be pulled up to 5.5V

even if VIO_IN is less than 5.5V.

nRESET

nRESET issues the main reset to the CPU/controller.

nRESET is immediately asserted low when either the

VIN voltage is above or below the UV or OV thresholds

or any valid output supply voltage is below its Power

Good threshold. After startup, nRESET de-asserts after

a programmable delay time when VIN and all outputs

are above their respective UVLO thresholds. The

nRESET delay time is controlled by the I2C bits

nRST_DLY[2:0], which programs the delay between

200us and 1ms in 114us steps. nRESET is configurable,

so refer to the CMI Options section in the back of the

datasheet for its specific functionality for each CMI.

nRESET is an open drain output and is 5.5V tolerant

meaning that nRESET can be pulled up to 5.5V even if

VIO_IN is less than 5.5V.

EXT_EN

EXT_EN is used to control an external regulator or to

provide a control signal to other system components.

Depending on the MODE pin status, EXT_EN is either

an exact output of the ACT8870’s internal BUCK1

enable signal or an exact output of the bypass switch

enable signal. The I2C bit EXT_EN_POL controls the

EXT_EN polarity. EXT_EN is active high when

EXT_EN_POL is low and EXT_EN is active low when

EXT_EN_POL is high. EXT_EN is a push-pull CMOS

output using VIO_IN supply. Note that the EXT_EN

output is enabled and valid in all modes of operation.

EXT_EN is configurable, so refer to the CMI Options

section in the back of the datasheet for its specific

functionality for each CMI.

PG signals the status of a regulator’s Power Good / UV

comparator. When the regulator is below the Power

Good threshold, the PG pin is pulled low. When above

the threshold, the PG pin is open drain. The PG

functionality is enabled by default, but can be disabled

by I2C.

Disable PG for each regulator using the

regulator’s UV_FLTMSK bit. PG is configurable, so

refer to the back of the datasheet for its specific

functionality for each CMI. PG is an open drain output

and is 5V tolerant meaning that PG can be pulled up to

5.5V even if VIO_IN is less than 5.5V.

Step-down dc/dc Converters

General Description

The ACT8870 contains four fully integrated step-down

converters. Buck1 is a 4A output, while Buck2, Buck3,

and Buck4 are 2.5A outputs. All buck converters are

fixed frequency, current-mode controlled, synchronous

PWM converters that achieve peak efficiencies of up to

96.5%. The buck converters switch at 2.25MHz and are

internally compensated, requiring only three small

external components (Cin, Cout, and L) for operation.

They ship with default output voltages that can be

modified via the I2C interface for systems that require

advanced power management functions.

ACT8870 Datasheet(PDF) 25 Page - Active-Semi, Inc

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