IP1202 datasheet(12/29 Pages) IRF

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iP1202

iP1202 Users Design Guidelines

The iP1202 can be configured as a dual channel 15A

or parallel single 30A power block consisting of opti-

mized power semiconductors, PWM control and its

associated passive components. It is based on a syn-

chronous buck topology and offers an optimized so-

lution where space, efficiency and noise caused by

parasitics are of concern. The phase shifted, two out-

put power block operates with fixed frequency volt-

age mode control and can be configured to operate

as a dual output or paralleled single output with cur-

rent sharing. The iP1202 components are integrated

in a ball grid array (BGA) package.

The input operating voltage range of the iP1202 is

5.5V to 13.2V. Both channels of the power block have

a common input.

Enabling the Outputs

The ENABLE pin turns on and turns off both outputs

of the iP1202 simultaneously. The iP1202 outputs will

be turned off by floating the ENABLE pin. ENABLE

low will start the outputs. The converter can also be

shutdown by pulling the soft-start pins to PGND

through a logic level MOSFET the drain of which con-

nects to the soft start pin (see Fig.12). This feature

can be useful if sequencing or different start-up tim-

ing of the outputs are required. In situations where

the output has undergone a latched shutdown due to

overvoltage or overcurrent, cycling ENABLE will re-

set the outputs. Cycling soft start pins will not unlatch

the outputs.

Dual Soft Start

The Soft Start function provides a controlled rise of

the output voltage, thus limiting the inrush current

during start-up. The iP1202 provides two indepen-

dent soft start functions. The soft start pins can be

connected to the soft start capacitors to provide dif-

ferent start-up and sequencing profiles.

Each soft start function has an internal 25uA +/-20%

current source that charges the external soft start

capacitor Css up to 3V. During power-up, the output

voltage starts ramping up only after the charging

voltage across the Css capacitor has reached a

0.8Vtyp threshold, as shown in Fig. 13.

Mode of Operation

The iP1202 can be configured to provide either two

independent dual outputs or single paralleled output

with current share. In dual output mode, the two error

amplifiers of the PWM controller operate indepen-

dently. Each output voltage of the iP1202 block is

controlled by its own error amplifier. The output of

the error amplifier and the internally generated ramp

signal are compared to produce PWM pulses of fixed

frequency that drive the internal power switches. In

this mode, the VP-ref pin must be connected to Vref

pin. Vref pin is the internally generated 0.8V refer-

ence input of first error amplifier . Refer to the inter-

nal block diagram of the iP1202 in Fig.1.

This threshold voltage should be taken into consid-

eration when designing sequencing profiles using

the iP1202 as it will effect start-up delays and ramp-

times.

For proper implementation of sequencing of outputs

using the iP1202, refer to IR Application Note AN-

1053 - Power sequencing techniques using iP1201

and iP1202.

Fig. 13: Power Up Threshold

0.8Vtyp

VCss

VOUT

Css

Iss

iP1202

SS1/SS2

Fig. 12: Soft Start/Enable Circuit

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