April 1998

5-93

MIC5010

Micrel

5

Applications Information

Functional Description (Refer to Block Diagram)

The various MIC5010 functions are controlled via a logic

block connected to the input pin 3. When the input is low all

functions are turned off for low standby current, and the gate

of the power MOSFET is also held low through 500

Ω to an

N-channel switch. When the input is taken above the turn-

on threshold (3.5V typical), the N-channel switch turns off

and the charge pump is turned on to charge the gate of the

power FET. A bandgap type voltage regulator is also turned

on which biases the current sense circuitry.

The charge pump incorporates a 100kHz oscillator and on-

chip pump capacitors capable of charging 1 nF to 5V above

supply in 60

µS typical. With the addition of 1nF capacitors

at C1 and C2, the turn-on time is reduced to 25

µS typical.

The charge pump is capable of pumping thegate up to over

twice the supply voltage. For this reason a zener clamp

(12.5V typical) is provided between the gate pin 8 and the

source pin 6 to prevent exceeding the V

MOSFET at high supplies.

The current sense operates by comparing the sense volt-

age at pin 5 to an offset version of the source voltage at pin

6. Current I4 flowing in threshold pin 4 is mirrored and

returned to the source via a 1k

Ω resistor to set the offset or

trip voltage. When (V

current sense trips and sets the current sense latch to turn

off the power FET. An integrating comparator is used to

reduce sensitivity to spikes on pin 5. The latch is reset to turn

the FET back on by “recycling” the input pin 3 low and then

high again.

A resistor R

An additional capacitor C

higher trip voltage at turn-on, which is necessary to prevent

high in-rush current loads such as lamps or capacitors from

false-tripping the current sense.

When the current sense has tripped, the fault pin 14 will be

high as long as the input pin 3 remains high. However, when

the input is low the fault pin will also be low.

Construction Hints

High current pulse circuits demand equipment and assem-

bly techniques that are more stringent than normal, low

current lab practices. The following are the sources of

common pitfalls encountered while prototyping:Supplies:

many bench power supplies have poor transient response.

Circuits that are being pulse tested, or those that operate by

pulse-width modulation will produce strange results when

used with a supply that has poor ripple rejection, or a

peaked transient response. Monitor the power supply volt-

age that appears at the drain of a high-side driver (or the

supply side of the load in a low-side driver) with an oscillo-

scope. It is not uncommon to find bench power supplies in

the 1kW class that overshoot or undershoot by as much as

50% when pulse loaded. Not only will the load current and

voltage measurements be affected, but it is possible to

over-stress various components—especially electrolytic

capacitors—with possibly catastrophic results. A 10

µF sup-

ply bypass capacitor at the chip is recommended.

+

-

V+

CHARGE

PUMP

TEMP

SENSE

V. REG

R

S

Q

LOGIC

MIC5010

3

14

71

4

6

5

8

9

10

11

13

500

Ω

1k

C1 Com C2

V+

Gate

Sense

Source

Ground

Inhibit

Threshold

Input

Fault

1k

+

-

I4

CURRENT

SENSE

LATCH

12.5V

Block Diagram