AD5426 datasheet(13/24 Pages) AD

13 / 24 page

REV. 0

AD5426/AD5432/AD5443

–13–

SYNC Function

SYNC is an edge-triggered input that acts as a frame synchroni-

zation signal and chip enable. Data can be transferred into the

device only while

SYNC is low. To start the serial data transfer,

SYNC should be taken low observing the minimum SYNC

falling to SCLK falling edge setup time, t4.

Daisy-Chain Mode

Daisy-chain is the default power-on mode. To disable the daisy-

chain function, write 1001 to control word. In daisy-chain mode

the internal gating on SCLK is disabled. The SCLK is continuously

applied to the input shift register when

SYNC is low. If more

than 16 clock pulses are applied, the data ripples out of the shift

the rising edge of SCLK (this is the default, use the control word

to change the active edge) and is valid for the next device on the

falling edge (default). By connecting this line to the DIN input on

the next device in the chain, a multidevice interface is constructed.

16 clock pulses are required for each device in the system. There-

fore, the total number of clock cycles must equal 16N where N is

the total number of devices in the chain. See the timing diagram

in Figure 3.

When the serial transfer to all devices is complete,

SYNC should

be taken high. This prevents any further data being clocked into

the input shift register. A burst clock containing the exact number

of clock cycles may be used and

SYNC taken high some time

later. After the rising edge of

SYNC, data is automatically trans-

ferred from each device’s input shift register to the addressed DAC.

When control bits = 0000, the device is in No Operation mode.

This may be useful in daisy-chain applications where the user

does not want to change the settings of a particular DAC in the

chain. Simply write 0000 to the control bits for that DAC and

the following data bits will be ignored.

Standalone Mode

After power-on, write 1001 to control word to disable daisy-chain

mode. The first falling edge of

SYNC resets a counter that counts

the number of serial clocks to ensure the correct number of bits

are shifted in and out of the serial shift registers. A rising edge on

SYNC during a write causes the write cycle to be aborted.

After the falling edge of the 16th SCLK pulse, data will automati-

cally be transferred from the input shift register to the DAC. For

another serial transfer to take place, the counter must be reset by

the falling edge of

SYNC.

CIRCUIT OPERATION

Unipolar Mode

Using a single op amp, these devices can easily be configured to

provide 2-quadrant multiplying operation or a unipolar output

voltage swing as shown in Figure 6.

When an output amplifier is connected in unipolar mode, the

output voltage is given by

OUT

REF

=×

–

where D is the fractional representation of the digital word

loaded to the DAC, and n is the number of bits.

D= 0 to 255 (8-bit AD5426)

= 0 to 1023 (10-bit AD5432)

= 0 to 4095 (12-bit AD5443)

Note that the output voltage polarity is opposite to the VREF

polarity for dc reference voltages.

These DACs are designed to operate with either negative or

positive reference voltages. The VDD power pin is used by

only the internal digital logic to drive the DAC switches’ on

and off states.

These DACs are also designed to accommodate ac reference

input signals in the range of –10 V to +10 V.

VOUT =

0 TO –VREF

SCLK SDIN

GND

VREF

SYNC

IOUT2

IOUT1

RFB

MICROCONTROLLER

AGND

AD5426/

AD5432/AD5443

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (1pF – 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

VREF

VDD

Figure 6. Unipolar Operation

With a fixed 10 V reference, the circuit shown in Figure 6 will

give a unipolar 0 V to –10 V output voltage swing. When VIN

is an ac signal, the circuit performs 2-quadrant multiplication.

Table II shows the relationship between digital code and expected

output voltage for unipolar operation (AD5426, 8-bit device).

Table II. Unipolar Code Table

Digital Input

Analog Output (V)

1111 1111

–VREF (255/256)

1000 0000

–VREF (128/256) = –VREF/2

0000 0001

–VREF (1/256)

0000 0000

–VREF (0/256) = 0

Bipolar Operation

In some applications, it may be necessary to generate full

4-quadrant multiplying operation or a bipolar output swing.

This can be easily accomplished by using another external

amplifier and some external resistors as shown in Figure 7. In

this circuit, the second amplifier A2 provides a gain of 2. Bias-

ing the external amplifier with an offset from the reference

voltage results in full 4-quadrant multiplying operation. The

transfer function of this circuit shows that both negative and

positive output voltages are created as the input data (D) is

incremented from code zero (VOUT = –VREF) to midscale

(VOUT = 0 V ) to full scale (VOUT = +VREF).

OUT

REF

=×









–

where D is the fractional representation of the digital word

loaded to the DAC and n is the resolution of the DAC.

D= 0 to 255 (8-bit AD5426)

= 0 to 1023 (10-bit AD5432)

= 0 to 4095 (12-bit AD5443)

When VIN is an ac signal, the circuit performs 4-quadrant

multiplication.

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