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3948 Datasheet(PDF) 5 Page - Allegro MicroSystems

Part # 3948
Description  DMOS FULL-BRIDGE PWM MOTOR DRIVER
PDF  12 Pages
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

3948 Datasheet(HTML) 5 Page - Allegro MicroSystems

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3948
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
www.allegromicro.com
5
FUNCTIONAL DESCRIPTION
Serial Interface. The A3948 is controlled via a 3-wire
(clock, data, strobe) serial port. The programmable
functions allow maximum flexibility in configuring the
PWM to the motor drive requirements. The serial data is
clocked in starting with D19.
Bit
Function
D0
Blank Time LSB
D1
Blank Time MSB
D2
Off Time LSB
D3
Off Time Bit 1
D4
Off Time Bit 2
D5
Off Time Bit 3
D6
Off Time MSB
D7
Fast Decay Time LSB
D8
Fast Decay Time Bit 1
D9
Fast Decay Time Bit 2
D10
Fast Decay Time MSB
D11
Sync. Rect. Mode
D12
Sync. Rect. Enable
D13
External PWM Mode
D14
Enable
D15
Phase
D16
Reference Range Select
D17
Internal PWM Mode
D18
Test Use Only
D19
Sleep Mode
D0 – D1 Blank Time. The current-sense comparator is
blanked when any output driver is switched on, according
to the table below. fosc is the oscillator input frequency.
D1
D0
Blank Time
0
0
4/fosc
0
1
6/fosc
1
0
12/fosc
1
1
24/fosc
D2 – D6 Fixed-Off Time. A five-bit word sets the
fixed-off time for internal PWM current control. The off
time is defined by
toff = (8[1 + N]/fosc) - 1/fosc
where N = 0 … 31
For example, with an oscillator frequency of 4 MHz, the
off time will be adjustable from 1.75
µs to 63.75 µs in
increments of 2
µs.
D7 – D10 Fast Decay Time. A four-bit word sets the
fast-decay portion of the fixed-off time for the internal
PWM control circuitry. This will only have impact if the
mixed-decay mode is selected (via bit D17 and the MODE
input terminal). For tfd > toff, the device will effectively
operate in the fast-decay mode. The fast decay portion is
defined by
tfd = (8[1 + N]/fosc) - 1/fosc
where N = 0 … 15
For example, with an oscillator frequency of 4 MHz, the
fast decay time will be adjustable from 1.75
µs to
31.75
µs in increments of 2 µs.
D11 Synchronous Rectification Mode. The active
mode prevents reversal of load current by turning off
synchronous rectification when a zero current level is
detected. The passive mode will allow reversal of current
but will turn off the synchronous rectifier circuit if the
load current inversion ramps up to the current limit set by
VREF/RS.
D11
Mode
0
Active
1
Passive
D12 Synchronous Rectification Enable.
D12
Synchronous Rect.
0
Disabled
1
Enabled
D13 External PWM Decay Mode. Bit D13 determines
the current-decay mode when using ENABLE chopping
for external PWM current control.
D13
Mode
0
Fast
1
Slow
D14 Enable Logic. Bit D14, in conjunction with
ENABLE, determines if the output drivers are in the
chopped (OFF)(ENABLE = D14) or ON (ENABLE
≠
D14) state.
ENABLE
D14
Mode
0
0
Chopped
10
On
01
On
1
1
Chopped



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