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ADAQ7980 Datasheet(PDF) 39 Page - Analog Devices

Part # ADAQ7980
Description  16-Bit, 1 MSPS, Integrated Data Acquisition Subsystem
PDF  49 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADAQ7980 Datasheet(HTML) 39 Page - Analog Devices

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Data Sheet
ADAQ7980/ADAQ7988
Rev. 0 | Page 39 of 49
3-WIRE CS MODE WITH THE BUSY INDICATOR
To connect a single ADAQ7980/ADAQ7988 to an SPI-compatible
digital host that has an interrupt input, use 3-wire CS mode
with the busy indicator.
Figure 73 shows the connection diagram, and Figure 74 shows
the corresponding timing.
With SDI tied to VIO, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. SDO
stays in high impedance until the completion of the conversion
irrespective of the state of CNV. Prior to the minimum conversion
time, use CNV to select other SPI devices, such as analog
multiplexers; however, return CNV to low before the minimum
conversion time elapses and then hold it low for the maximum
conversion time to guarantee the generation of the busy signal
indicator.
When the conversion completes, SDO goes from high impedance
to low impedance. With a pull-up on the SDO line, use this
transition as an interrupt signal to initiate the data reading
controlled by the digital host. The ADAQ7980/ADAQ7988 then
enter the acquisition phase and power down. The data bits clock
out, MSB first, by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can capture the
data, a digital host using the SCK falling edge allows a faster
reading rate if it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
If selecting multiple ADAQ7980/ADAQ7988 devices at the
same time, the SDO output pin handles this contention without
damage or induced latch-up. Meanwhile, it is recommended to
keep this contention as short as possible to limit extra power
dissipation.
ADAQ7980/
ADAQ7988 SDO
SDI
DATA IN
IRQ
DIGITAL HOST
CONVERT
CLK
VIO
VIO
47kΩ
CNV
SCK
Figure 73. 3-Wire CS Mode with the Busy Indicator Connection Diagram
(SDI = 1, High)
tCONV
tCNVH
tCYC
ACQUISITION
ACQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SCK
CNV
SDI = 1
SDO
D15
D14
D1
D0
tHSDO
12
3
15
16
17
tDSDO
tDIS
Figure 74. 3-Wire CS Mode with the Busy Indicator Serial Interface Timing (SDI = 1, High)



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