ADAQ7980 datasheet(28/49 Pages) AD

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ADAQ7980/ADAQ7988

Data Sheet

Rev. 0 | Page 28 of 49

ADC DRIVER INPUT

The ADC driver of the ADAQ7980/ADAQ7988 features a −3 dB

bandwidth of 35 MHz and a slew rate of 110 V/μs at G = +1

and VAMP_OUT = 2 V step. It features an input voltage noise of

5.9 nV/√Hz .The driver can operate over a supply voltage range

of 3.8 V to 10 V and consumes only 500 μA of supply current at a

supply difference of 5 V. The low end of the supply range allows

−5% variation of a 4 V supply. The amplifier is unity-gain stable,

and the input structure results in an extremely low input voltage

noise 1/f corner. The ADC driver uses a slew enhancement

architecture, as shown in Figure 55. The slew enhancement

circuit detects the absolute difference between the two inputs. It

then modulates the tail current, ITAIL, of the input stage to boost

the slew rate. The architecture allows a higher slew rate and a

faster settling time with a low quiescent current while maintaining

low noise. The user has access to all three amplifier signal pins,

providing flexibility to adapt to the desired application or

configuration.

IN+

VIN+

VIN–

V+

INPUT

STAGE

TO DETECT

ABSOLUTE

VALUE

SLEW ENHANCEMENT CIRCUIT

ITAIL

IN–

Figure 55. ADC Driver Slew Enhancement Circuit

INPUT PROTECTION

The amplifier is fully protected from ESD events, withstanding

human body model ESD events of 4000 V and field induced

charged device model events of 1250 V with no measured

performance degradation. The precision input is protected with

an ESD network between the power supplies and diode clamps

across the input device pair, as shown in Figure 56.

IN+

ESD

V–

V+

BIAS

TO THE REST OF THE AMPLIFIER

IN–

ESD

Figure 56. ADC Driver Input Stage and Protection Diodes

For differential voltages more than approximately 1.2 V at room

temperature and 0.8 V at 125°C, the diode clamps begin to

conduct. If large differential voltages must be sustained across

the input terminals, the current through the input clamps must

be limited to less than 10 mA. External series input resistors that

are sized appropriately for the expected differential overvoltage

can provide the needed protection.

The ESD clamps begin to conduct for input voltages that are

more than 0.7 V above the positive supply and input voltages

more than 0.7 V below the negative supply. If an overvoltage

condition is expected, the input current must be limited to less

than 10 mA.

Along with the ADC driver inputs, protection is also provided on

the ADC input. As shown in Figure 1, the ADAQ7980/ADAQ7988

house an RC filter between the ADC driver and the ADC. The

series resistor in this low-pass filter acts to limit current in an

overvoltage condition. The current sink capability of the reference

buffer works to hold the reference node at its desired value when

the ADC input protection diodes conduct due to an overvoltage

event.

Figure 57 shows an equivalent ADC analog input circuit of the

ADAQ7980/ADAQ7988.

The two diodes, D1 and D2, provide ESD protection for the ADC

inputs. Take care to ensure that the ADC analog input signal

never exceeds the reference value by more than 0.3 V or drops

below ground by more than 0.3 V because this causes diodes to

become forward-biased and start conducting current. These diodes

can handle a forward-biased current greater than or equal to the

short-circuit current of the ADC driver. For instance, these

conditions can occur when the ADC driver positive supply is

greater than the reference value. In such a case (for example, an

input buffer with a short circuit), use the current limitation to

protect the devices.

REF

RIN

CIN

IN+

OR IN–

GND

CPIN

Figure 57. Equivalent ADC Analog Input Circuit

The analog input structure allows the sampling of the true

differential signal between the ADC input pins. By using these

differential inputs, signals common to both inputs are rejected.

NOISE CONSIDERATIONS AND SIGNAL SETTLING

The ADC driver of the ADAQ7980/ADAQ7988 is ideal for

driving the on-board high resolution SAR ADC. The low input

voltage noise and rail-to-rail output stage of the driver helps to

minimize distortion at large output levels. With its low power of

500 μA, the amplifier consumes power that is compatible with

the low power SAR ADC. Furthermore, the ADC driver supports a

single-supply configuration; the input common-mode range

extends to the negative supply, and 1.3 V below the positive

supply.

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