1.3.2 LOCK DETECT OUTPUT CHARACTERISTICS

Output provided to indicate when the VCO frequency is in “lock.” When the loop is locked and the open drain lock detect mode

is selected, the pin’s output is HIGH, with narrow pulses LOW. When digital lock detect is selected, the output will be HIGH when

value of R[19]. Once lock is detected the output stays HIGH unless the absolute phase error exceeds 30 ns for a single reference

cycle. Setting the charge pump to TRI-STATE or power down (bits F2, F18) will reset the digital lock detect to the unlocked state.

The LD precision bit, R[19], will select five consecutive reference cycles, instead of three, for entering the locked state when R[19]

= HIGH.

1.3.3 LOCK DETECT FILTER CALCULATION

The component values for the open drain lock detect filter can be determined after assessing the qualifications for an in-lock con-

dition. The in-lock condition can be specified as being a particular number (N) of consecutive reference cycles or duration (D)

wherein the phase detector phase error is some factor less than the reference period. In an example where the phase detector

reference period is 10 kHz, one might select the threshold for in-lock as occurring when 5 consecutive phase comparisons have

elapsed where the phase errors are a 1000 times shorter than the reference period (100 ns). Here, N = 5 and F = 1000.

For the lock detect filter shown in

Figure 1, when used in conjunction with a open drain (active sink only) lock detect output, the

erence cycle period, its “effective” resistance would be on par with R2. The two resistors for that duty cycle condition on average

appear to be two 1000x R1 resistors connected across the supply voltage with their common node voltage (Vc) at V

errors larger than 1/1000th of the reference cycle period would drag the average voltage of node Vc below V

node Vc would fall below V

1.3.4 FastLock MODES

FastLock enables the designer to achieve both fast frequency transitions and good phase noise performance by dynamically

changing the PLL loop bandwidth. The FastLock modes allow wide band PLL fast locking with seemless transition to a low phase

noise narrow band PLL. Consistent gain and phase margins are maintained by simultaneously changing charge pump current

magnitude, counter values, and loop filter damping resistor. The four FastLock modes in

Table 5 are similar to the technique used

in National Semiconductor’s LMX 233X series Dual Phase Locked Loops and are selected by F9, F10, and N19 when F8 is HIGH.

Modes 1 and 2 change loop bandwidth by a factor of two while modes 3 and 4 change the loop bandwidth by a factor of 4. Modes

1 and 2 increase charge pump magnitude by a factor of 4 and should use R2’=R2 for consistent gain and phase margin. Modes

sistent stability margin in modes 3 and 4. When F8 is LOW, the FastLock modes are disabled, F9 controls only the FL

level (FL

1 mA).

DS100127-13

FIGURE 1. Typical Lock Detect Circuit

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