LM2326 datasheet(17/19 Pages) NSC

17 / 19 page

1.7 Application Information (Continued)

1.7.9 FastLock MODE 1 PROGRAMMING

The F[1]–F[7] bits will be denoted as (*) and are dependent on the desired modes of the applicable functions. To program the de-

vice for mode 1 FastLock, the F[8]–F[10] bits are programmed 100, while the N[19] bit is set to 1. The device will stay in the 4X

current mode until another N bit stream is sent with the N[19] bit reset to 0. This gives a bit stream as follows:

1.7.10 FastLock MODE 2 PROGRAMMING

Again, the F[1]–F[7] bits will be denoted as don’t care (*) but are dependent on the desired modes of the applicable functions.

To program the device for mode 2 FastLock, the F[8]–F[10] bits are programmed 101, while the N[19] bit is set to 1. The device

will stay in the 4X current mode for the programmed number of phase detector cycles. Bits F[11]–F[14] program this number of

cycles and are shown in

Table 6. For our example, we will use 27 phase detector cycles, i.e. bits F[11]–F[14] will be 0110

b. After

27 phase detector cycles, the N[19] bit returns to zero, bringing the device back to low current mode. The resulting bit stream is

as follows:

FastLock modes 3 and 4 are programmed in the same manner and give the added 4X gain increase as discussed in Section 1.3.4

FastLock modes.

DS100127-17

DS100127-18

LM2326 Datasheet(PDF) 17 Page - National Semiconductor (TI)