LMX2502 datasheet(7/18 Pages) NSC

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Functional Description

GENERAL DESCRIPTION

LMX2502/12 is a highly integrated frequency synthesizer

system that generates LO signals for PCS and Cellular

CDMA applications. These devices include all the functional

blocks of a PLL, RF VCO, prescaler, RF phase detector, and

loop filter. The need for external components is limited to a

few passive elements for matching the output impedance

and bypass elements for power line stabilization.

In addition to the RF circuitry, the IC also includes IF fre-

quency dividers, and an IF phase detector to complete the IF

synthesis with the external VCO and the loop filter. Table 1

summarizes the counter values used to generate the default

IF frequencies.

Using a low spurious fractional-N synthesizer based on a

delta sigma modulator, the circuit can support 10 kHz chan-

nel spacing for PCS and Cellular CDMA systems.

The fractional-N synthesizer enables faster lock time, which

reduces power consumption and system set-up time. Addi-

tionally, the loop filter occupies a smaller area as opposed to

the integer-N architecture. This allows the loop filter to be

embedded into the circuit, minimizing the external noise

coupling and total form factor. The delta sigma architecture

delivers very low spurious, which can be a significant prob-

lem for other PLL solutions.

The circuit also supports commonly used reference frequen-

cies of 19.20 MHz and 19.68 MHz.

FREQUENCY GENERATION

RF-PLL Section

The divide ratio can be calculated using the following equa-

tion:

LMX2502 – PCS CDMA:

VCO = {8 x RF_B + RF_A + (RF_FN / fOSC)x10

4}xf

OSC

where (RF_A < RF_B)

LMX2512 – Cellular CDMA:

VCO = {6 x RF_B + RF_A + (RF_FN / fOSC)x10

4}xf

OSC

where (RF_A < RF_B)

where

VCO: Output frequency of voltage controlled oscillator (VCO)

RF_B: Preset divide ratio of binary 4-bit programmable

counter (2

≤ RF_B ≤ 15)

RF_A: Preset divide ratio of binary 3-bit swallow counter (0

≤

RF_A

≤ 7 for LMX2502 or 0 ≤ RF_A ≤ 5 for LMX2512)

RF_FN: Preset numerator of binary 11-bit modulus counter

≤ RF_FN < 1920 for f

OSC = 19.20 MHz or 0

≤ RF_FN <

1968 for f

OSC = 19.68 MHz)

OSC: Reference oscillator frequency

IF-PLL Section

VCO = {16 x IF_B + IF_A} x fOSC / IF_R where (IF_A < IF_B)

where

VCO: Output frequency of the voltage controlled oscillator

(VCO)

IF_B: Preset divide ratio of the binary 9-bit programmable

counter (1

≤ IF_B ≤ 511)

IF_A: Preset divide ratio of the binary 4-bit swallow counter

≤ IF_A ≤ 15)

OSC: Reference oscillator frequency

IF_R: Preset divide ratio of the binary 9-bit programmable

reference counter (2

≤ IF_R ≤ 511)

From the above equation, the LMX2502/12 generates the

fixed IF frequencies as summarized in Table 1.

TABLE 1. IF Frequencies

Device Type

VCO

(MHz)

IF_B

IF_A

OSC/IF_R

(kHz)

LMX2502LQ1635

440.76

229

120

LMX2512LQ0967

170.67

120

LMX2512LQ1065

367.20

191

120

VCO FREQUENCY TUNING

The center frequency of the RF VCO is determined by the

resonant frequency of the tank circuit. This tank circuit is

implemented on-chip and requires no external inductor. The

LMX2502/12 actively tunes the tank circuit to the required

frequency with the built-in tracking algorithm.

BANDWIDTH CONTROL AND FREQUENCY LOCK

During the frequency acquisition period, the loop bandwidth

is significantly extended to achieve frequency lock. Once

frequency lock occurs, the PLL will return to a steady state

condition with the loop bandwidth set to its nominal value.

The transition between acquisition and lock modes occurs

seamlessly and extremely fast, thereby, meeting the strin-

gent requirements associated with lock time and phase

noise. Several controls (BW_DUR, BW_CRL, and BW_EN)

are used to optimize the lock time performance.

SPURIOUS REDUCTION

To improve the spurious performance of the device one of

two types of spurious reduction schemes can be selected:

•

A continuous optimization scheme, which tracks the en-

vironmental and voltage variations, giving the best spuri-

ous performance over changing conditions

•

A one time optimization scheme, which sets the internal

compensation values only when the PLL goes into a

locked state.

The spurious reduction can also be disabled, but it is recom-

mended that the continuous optimization mode be used for

normal operation.

POWER DOWN MODE

The LMX2502 and LMX2512 include a power down mode to

reduce the power consumption. The LMX2502/12 enters into

the power down mode either by taking the CE pin LOW or by

setting the power down bits in Register R1. Table 2 summa-

rizes the power down function. If CE is set LOW, the circuit is

powered down regardless of the register values. When CE is

HIGH, the IF and RF circuitry are individually powered down

by setting the register bits.

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