LMX2502 datasheet(8/18 Pages) NSC

8 / 18 page

Functional Description (Continued)

TABLE 2. Power Down Configuration

CE Pin

RF_EN

IF_EN

RF Circuitry

IF Circuitry

OFF

X = Don’t care.

LOCK DETECT

The LD output can be used to indicate the lock status of the

RF PLL. Bit 21 in Register R0 determines the signal that

appears on the LD pin. When the RF PLL is not locked, the

LD pin remains LOW. After obtaining phase lock, the LD pin

will have a logical HIGH level. The output can also be

programmed to be ground at all times.

TABLE 3. Lock Detect Modes

LD Bit

Mode

Disable (GND)

Enable

TABLE 4. Lock Detect Logic

RF PLL Section

LD Output

Locked

HIGH

Not Locked

LOW

Note 9: LD output becomes LOW when the phase error is larger than tW2.

Note 10: LD output becomes HIGH when the phase error is less than tW1 for

four or more consecutive cycles.

Note 11: Phase Error is measured on leading edge. Only errors greater than

tW1 and tW2 are labeled.

Note 12: tW1 and tW2 are equal to 10 ns.

Note 13: The lock detect comparison occurs with every 64th cycle of fR and

fN.

20068005

FIGURE 1. Lock Detect Timing Diagram Waveform (Notes 9, 10, 11, 12, 13)

LMX2502 Datasheet(PDF) 8 Page - National Semiconductor (TI)