TLK1521

500 Mbps to 1.3 Gbps TRANSCEIVER

SLLS591A− OCTOBER 2003 − REVISED JANUARY 2004

6

POST OFFICE BOX 655303

data reception latency

The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output

in the aligned parallel word with RXD0 received as first bit. The receive latency is fixed once the link is

established. However, due to silicon process variations and implementation variables such as supply voltage

and temperature, the exact delay varies slightly. Figure 5 illustrates the timing relationship between the serial

receive pins, the recovered word clock (RX_CLK), and the receive data bus.

18-Bit Decoded Word

20-Bit Encoded Word

DINTXP,

DINTXN

RXD(0−17)

RX_CLK

R(latency)

Figure 5. Receiver Latency

serial-to-parallel

Serial data is received on the DINRXP and DINRXN pins. The interpolator and clock recovery circuit locks to

the data stream if the clock to be recovered is within

±100 PPM of the internally generated bit rate clock. The

recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel

shift registers.

synchronization mode

The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be

accomplished in one of two ways.

rapid synchronization

The serializer has the capability to send specific SYNC patterns consisting of nine ones and nine zeros,

switching at the input clock rate. The transmission of SYNC patterns enables the deserializer to lock to the

serializer signal within a deterministic time frame. The transmission of SYNC patterns is selected via the SYNC

input on the serializer. Upon receiving a valid SYNC pulse (wider than 6 clock cycles), 1024 cycles of SYNC

pattern are sent.

When the deserializer detects edge transitions at the serial input, it attempts to lock to the embedded clock

information. The deserializer LOCKB output remains inactive while its clock/data recovery (CDR) locks to the

incoming data or SYNC patterns present on the serial input. When the deserializer locks to the serial data, the

LOCKB output goes active. When LOCKB is active, the deserializer outputs represent incoming serial data. One

approach is to tie the deserializer LOCKB output directly to the SYNC input of the transmitter. This assures that

enough SYNC patterns are sent to achieve deserializer lock.

random lock synchronization

The deserializer can attain lock to a data stream without requiring the serializer to send special SYNC patterns.

This allows the TLK1521 to operate in open-loop applications. Equally important is the deserializer’s ability to

support hot insertion into a running backplane. In the open-loop or hot-insertion case, it is assumed the data

stream is essentially random. Therefore, because lock time varies due to data stream characteristics, the exact

lock time cannot be predicted. The primary constraint on the random lock time is the initial phase relation

between the incoming data and the GTX_CLK when the deserializer powers up.