FEDL9484-01

ML9484

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Switching Characteristics



OSC timing

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable pin

OSC IN clock frequency

(External input)

0.5

1.8

10

kHz

OSC

Clock pulse width

(External input)

40

—

—

μs

OSC

Clock rise and fall time

(External input)

Clock input from OSC.

OSC I/E = "L"

—

—

(*1)

μs

OSC

Internal clock frequency

(Internal oscillation)

OSC open.

(F2, F1, F0)=(0, 0, 1)

OSC I/E = "H"

18

28.8

44

kHz

OSC

The relation between OSC IN clock frequency and frame frequency is as the equation below.

The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.

Make the rise as steep as possible.

Reference value: max=2μs.



Serial interface timing

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable pin

Data clock frequency

0.01

—

1

MHz CLOCK

Data clock pulse width

100

—

—

ns

CLOCK

Data setup time

50

—

—

ns

DATA

Data hold time

50

—

—

ns

CLOCK

CLOCK-LOAD timing

100

—

—

ns

CLOCK

LOAD-CLOCK timing

100

—

—

ns

LOAD

LOAD pulse width

100

—

—

ns

LOAD

Signal rise and fall time

tsr,tsf

—

—

(*2)

ns



CLOCK,DATA,

LOAD

(*2) tsr and tsf shall be reference values.

The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.

Make the rise as steep as possible.

Reference value: max=10ns.