8

ATSAM9703

1710C–DRMSD–12/02

Timings

capacitance = 30 pF, crystal frequency or external clock at X1 = 9.6 MHz.

External ROM Timing

Figure 4. ROM Read Cycle

External RAM Timing

Figure 5. 16-bit SRAM Read Cycle

WCS0

WA[24:0]

WOE

WD[15:0]

t

CSOE

t

RC

t

POE

t

OE

t

DF

t

ACE

Table 9. Timing Parameters

Symbol

Parameter

Min

Typ

Max

Unit

Read Cycle Time

130

ns

t

CSOE

Chip Select Low/Address Valid to WOE low

45

80

ns

t

POE

Output Enable Pulse Width

78

ns

t

ACE

Chip Select/Address Access Time

125

ns

Output Enable Access Time

70

ns

Chip select or WOE High to Input Data High-Z

0

50

ns

WCS1

WA[24:0]

WWE

WOE

WD[15:0]

t

CSOE

t

RC

t

POE

t

OE

t

DF

t

ACE