S2-LP datasheet(25/90 Pages) STMICROELECTRONICS

25 / 90 page

S2-LP

Specifications

DocID029944 Rev 1

25/90

4.9.3

Harmonic emission at 915 MHz

Table 29: Harmonic emission at 915 MHz

Parameter

Test conditions

SMPS on

Unit

dBm

-46

-55

-46

-49

-48

-51

4.10

Digital interface specification

Table 30: Digital SPI input, output and GPIO specification

Parameter

Test condition

Min.

Typ.

Max.

Unit

SPI clock frequency

MHz

Port I/O capacitance

1.4

Rise time

From 0.1*VDD to 0.9*VDD, CL=20

pF (low output current

programming)

6.0

From 0.1*VDD to 0.9*VDD, CL=20

pF (high output current

programming)

2.5

Fall time

From 0.1*VDD to 0.9*VDD, CL=20

pF (low output current

programming)

7.0

From 0.1*VDD to 0.9*VDD, CL=20

pF (high output current

programming)

2.5

Logic high level input

voltage

VDD/2

+0.3

Logic low level input

voltage

VDD/8

+0.3

High level output voltage

IOH = -2.4 mA (-4.2 mA into high

output current mode).

(5/8)*

VDD+

0.1

Low level output voltage

IOL = +2.0 mA (+4.0 mA into high

output current mode).

0.5

CSn low to positive edge

on SCLK in ready state

µs

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