S2-LP datasheet(38/90 Pages) STMICROELECTRONICS

38 / 90 page

Block description

S2-LP

38/90

DocID029944 Rev 1

below the low threshold for all the duration of such period, then the attenuation is

decreased.

The actual time is

�� =

��

∙ 2��_�� , ranging from about 0.5µs to about 15ms.

For frequency modulation, the measurement time is normally set to a few µs in order to

achieve fast settling of the algorithm.

For amplitude, to avoid an unstable behavior, the measure time must be larger than the

duration of the longest train of ‘0’ symbols expected during the preamble/synchronization

word.

The default value for such parameter is 0x2.

Hold time: this parameter sets a wait time for the algorithm to let the signal level to settle

after a change in the attenuation level.

The actual time is

��ℎ�� =

��

∙ ��_��, ranging from about 0.5 µs to about 32 µs.

The recommended setting for such parameter is 0x0C.

AGC enable: enables the AGC algorithm.

Freeze on sync: freeze the AGC level after when the sync word has been received.

5.5.3

Symbol timing recovery

The S2-LP supports two different algorithms for the timing recovery. The selection of the

algorithm is done with the register CLOCK_REC_ALGO_SEL.



If CLOCK_REC_ALGO_SEL = 0, then a simple first order algorithm is used (shortly

referred to as DLL).



If CLOCK_REC_ALGO_SEL = 1, then a second order algorithm is used (shortly

referred to as PLL).

5.5.3.1

DLL mode

The DLL algorithm, being based on a first order loop, is only able to control the delay of the

local bit-timing generator in order to align it to the received bit period. If there is an error

between the actual received bit period and the nominal one, the relative edges will drift

over time and the algorithm will periodically apply a delay correction to recover. Since in

presence of long sequences of zeroes or ones it is not possible to estimate any timing

error, the loop tends to lose lock if the period error is large (greater than 3%).

The convergence speed of the loop is controlled by the CLK_REC_P_GAIN_FAST/SLOW

parameter (KP) in the CLOCKREC1 and CLOCKREC2 registers with a smaller value

yielding a faster loop. Allowed values for KP are from 0 to 7. The optimal values obtained

for all modulations and data rates are KP = 1 or KP = 2.

The setting of the following registers also affects the behavior of the clock recovery

algorithms.



Post-filter length: this parameter controls the length of the demodulator post-filter

(CLOCKREC register). Setting this value to 1B may improve demodulation

performance but requires a slower recovery. The recommended value for such

parameter is 0B.



RSSI threshold: this parameter sets the minimum signal power above which the timing

recovery is started (RSSI_TH register).

S2-LP Datasheet(PDF) 38 Page - STMicroelectronics

S2-LP Datasheet(HTML) 38 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

Datasheet Download

Link URL