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SC16C752B Datasheet(PDF) 34 Page - NXP Semiconductors |
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SC16C752B Datasheet(HTML) 34 Page - NXP Semiconductors |
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34 / 47 page  Philips Semiconductors SC16C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Product data Rev. 03 — 14 December 2004 34 of 47 9397 750 14443 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. [3] These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150 °C. The customer is responsible for verifying junction temperature. [4] These parameters apply for D7-D0. [5] These parameters apply for DTRA, DTRB, INIA, INTB, RTSA, RTSB, RXRDYA, RXRDYB, TXRDYA, TXRDYB, TXA, TXB. [6] Measurement condition, normal operation other than sleep mode: VCC = 3.3 V; Tamb =25 °C. Full duplex serial activity on all two serial (UART) channels at the clock frequency specified in the recommended operating conditions with divisor of 1. [7] Except x2, VOL = 1 V typical. [8] Applies to external clock; crystal oscillator max. 24 MHz. 11. Dynamic characteristics Table 26: AC electrical characteristics Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V ± 10% or 5 V ± 10%, unless specified otherwise. Symbol Parameter Conditions 2.5 V 3.3 V and 5 V Unit Min Max Min Max td1 IOR delay from chip select 10 - 0 - ns td2 read cycle delay 25 pF load 20 - 20 - ns td3 delay from IOR to data 25 pF load - 77 - 26 ns td4 data disable time 25 pF load - 15 - 15 ns td5 IOW delay from chip select 10 - 10 - ns td6 write cycle delay 25 - 25 - ns td7 delay from IOW to output 25 pF load - 100 - 33 ns td8 delay to set interrupt from modem input 25 pF load - 100 - 24 ns td9 delay to reset interrupt from IOR 25 pF load - 100 - 24 ns td10 delay from stop to set interrupt - 1 - 1 Rclk baud rate td11 delay from IOR to reset interrupt 25 pF load - 100 - 29 ns td12 delay from start to set interrupt - 100 - 100 ns td13 delay from IOW to transmit start 8 24 8 24 Rclk baud rate td14 delay from IOW to reset interrupt - 100 - 70 ns td15 delay from stop to set RXRDY - 1- 1Rclk baud rate td16 delay from IOR to reset RXRDY - 100 - 75 ns td17 delay from IOW to set TXRDY - 100 - 70 ns td18 delay from start to reset TXRDY- 16 - 16 Rclk baud rate td19 delay between successive assertion of IOW and IOR - 20 - 20 ns th1 chip select hold time from IOR 0 - 0 - ns th2 chip select hold time from IOW 0 -0 -ns th3 data hold time 15 - 15 - ns th4 address hold time 0 - 0 - ns th5 hold time from XTAL1 clock HIGH-to-LOW transition to IOW or IOR release 20 - 20 - ns |
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