DM8147SCIS0 datasheet(11/377 Pages) TI1

11 / 377 page

TMS320DM8148, TMS320DM8147

www.ti.com

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Table 8-66, Compatible JEDEC DDR3 Devices (Per Interface):

Section 8.13.4.2.4.1

Compatible JEDEC DDR3 •

Updated/Changed the max clock rate in footnote, "DDR3 devices with speed...." from "400" MHz to

Devices

"533" MHz

Table 8-78, Timing Requirements for McASP:

Section 8.14.3

•

Updated/Changed McASP1 Only ACLKR/X ext out, MIN value for NO. 5, tsu(AFSRX-ACLKRX), Setup

McASP (McASP[5:0])

time, MCA[x]_AFSR/X input valid before MCA[X]_ACLKR/X from "4" to "2" ns.

Electrical Data/Timing

•

Updated/Changed McASP1 Only ACLKR/X ext out, MIN value for NO. 7,tsu(AXR-ACLKRX), Setup

time, MCA[x]_AXR input valid before MCA[X]_ACLKR/X from "4" to "2" ns.

Table 8-80, McBSP Registers:

Section 8.15

•

Updated/Changed McBSP HEX ADDRESS range from "0x4700 0000 - 0x4700 00C0" to "0x4700

Multichannel Buffered

0100 – 0x4700 01C0" (DDR_REG to STATUS_REG)

Serial Port (McBSP)

•

Added McBSP registers in HEX ADDRESS range "0x4700 0000 – 0x4700 004C" (REVNB to

DMATXWAKE_EN)

Section 9.1.2

Figure 9-1, Device Nomenclature:

Device and Development- •

Added "D = -40ºC to 90ºC, Industrial Temperature" to the TEMPERATURE RANGE area

Support Tool

Nomenclature

Contents

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DM8147SCIS0 Datasheet(PDF) 11 Page - Texas Instruments