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TMS320VC5470 Datasheet(PDF) 52 Page - Texas Instruments |
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TMS320VC5470 Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 93 page  MCU Subsystem Functional Overview 42 December 2001 – Revised December 2002 SPRS017B Some tools that only understand one type of processor may be configured for use with 5470 even when other devices are on the ASIC scan chain. This is done by instructing the tools to place the other “unrecognized” devices on the JTAG scan chain in their “BYPASS” modes. While the exact configuration methods are beyond the scope of this document, the key is to understand the length of the instruction registers for the TAP controllers so that the correct BYPASS instructions can be issued. For the 5470, this methodology would only apply to the 5470 emulation mode where all three TAP controllers are in the JTAG scan chain (EMU1 = EMU0 = ’1’ at TRST rising edge). The JTAG TAP controller instruction register lengths are listed in Table 4–8. Table 4–8. JTAG TAP Controller Instruction Register Lengths INSTRUCTION REGISTER LENGTH JTAG TAP CONTROLLER 4 bits ARM7TDMIE core 8 bits C54x DSP core 8 bits ASIC Logic TAP Controller |
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