VT82C586B datasheet(35/69 Pages) ETC

35 / 69 page

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VT82C586B

Revision 1.0 May 13, 1997

-29-

Offset 48 - Miscellaneous Control 3.................................RW

7-6

Reserved

........................................ always reads 0

MASTER# Pin Function (Pin 137) ... (3041 Silicon)

"Input" Mode (Pin 137 = MASTER#) ...default

"Output" Mode (Pin 137 = SDDIR)

IRQ8# Input Source.........(3040F and 3041 Silicon)

IRQ8# input on RTCX1 pin 104 ............default

IRQ8# input on KEYLOCK pin 106

See also Rx5A[2] - internal/external RTC:

Rx5A[2] Rx48[4] Pin Function

Ext RTC, IRQ8# in pin 104

Ext RTC, IRQ8# in pin 106

Int RTC, no IRQ8# in req'd

Extra RTC Port 74/75 Enable

Disable ...................................................default

Enable

Integrated USB Controller Disable

Enable.....................................................default

Disable

Integrated IDE Controller Disable

Enable.....................................................default

Disable

512K PCI Memory Decode

Use Rx4E[15-12] to select top of PCI memory

Use contents of Rx4E[15-12] plus 512K as top

of PCI memory .......................................default

Offset 4A - IDE Interrupt Routing ..................................RW

Wait for PGNT Before Grant to ISA Master /

DMA

Disable ...................................................default

Enable (must be set to 1)

Bus Select for Access to I/O Devices Below 100h

Access ports 00-FFh via XD bus............default

Access ports 00-FFh via SD bus (applies to

external devices only; internal devices such as

the mouse controller are not effected)

5-4

Reserved (do not program) ..................... default = 0

3-2

IDE Second Channel IRQ Routing

00 IRQ14

01 IRQ15.....................................................default

10 IRQ10

11 IRQ11

1-0

IDE Primary Channel IRQ Routing

00 IRQ14.....................................................default

01 IRQ15

10 IRQ10

11 IRQ11

4C - ISA DMA/Master Memory Access Control 1 ........ RW

7-0

PCI Memory Hole Bottom Address

These bits correspond to HA[23:16] ............ default=0

4D - ISA DMA/Master Memory Access Control 2 ........ RW

7-0

PCI Memory Hole Top Address (HA[23:16])

These bits correspond to HA[23:16] ............ default=0

Note:

Access to the memory defined in the PCI memory

hole will not be forwarded to PCI. This function is

disabled if the top address less than or equal to the

bottom address.

4F-4E - ISA DMA/Master Memory Access Control 3 ... RW

15-12 Top of PCI Memory for ISA DMA/Master accesses

0000 1M

.................................................... default

0001 2M

...

1111 16M

Note:

All ISA DMA / Masters that access addresses higher

than the top of PCI memory will not be directed to the

PCI bus.

Forward E0000-EFFFF Accesses to PCI........def=0

Forward A0000-BFFFF Accesses to PCI .......def=0

Forward 80000-9FFFF Accesses to PCI ........def=1

Forward 00000-7FFFF Accesses to PCI ........def=1

Forward DC000-DFFFF Accesses to PCI ......def=0

Forward D8000-DBFFF Accesses to PCI ......def=0

Forward D4000-D7FFF Accesses to PCI .......def=0

Forward D0000-D3FFF Accesses to PCI .......def=0

Forward CC000-CFFFF Accesses to PCI .....def=0

Forward C8000-CBFFF Accesses to PCI ......def=0

Forward C4000-C7FFF Accesses to PCI .......def=0

Forward C0000-C3FFF Accesses to PCI .......def=0

VT82C586B Datasheet(PDF) 35 Page - List of Unclassifed Manufacturers

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