VT82C586B datasheet(49/69 Pages) ETC

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VT82C586B

Revision 1.0 May 13, 1997

-43-

Power Management Subsystem Overview

The power management function of the VT82C586B is

indicated in the following block diagram:

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Figure 4. Power Management Subsystem Block Diagram

Refer to ACPI Specification v0.9 and APM specification v1.2

for additional information.

Power Plane Management

There are three power planes inside the VT82C586B.

The

scheme is optimal for systems with ATX power supplies,

although it also works using non-ATX power supplies. The

key feature of the ATX power supply is that two sets of power

sources are available: the first set is always on unless turned

off by the mechanical switch.

Only one voltage (5V) is

available for this set. The second set includes the normal 5V

and 12V and is controlled by an input signal PWRON as well

as the mechanical switch. This set of voltages is available only

when both the mechanical switch is on and the PWRON signal

is high. The power planes powered by the above two sets of

supplies are referred to as VDD-5VSB and VDD-5V (also

called VDD5), respectively.

In addition to the two power

planes, a third plane is powered by the combination of 5VSB

and VBAT for the integrated real time clock.

Most of the

circuitry inside the VT82C586B is powered by VDD-5V. The

amount of logic powered by VDD-5VSB is very small and

remains functional as long as the mechanical switch of the

power supply is turned on. The main function of this logic is

to control the power supply of the VDD-5V plane.

General Purpose I/O Ports

As ACPI compliant hardware, the VT82C586B includes

PWRBTN# (pin 91) and RI# (pin 93) pins to implement power

button and ring indicator functionality. In addition, a PWRON

pin (pin 107) is also available to control the VDD-5V power

plane by VDD-5VSB powered logic.

Furthermore, the

VT82C586B offers many general purpose I/O ports with the

following capabilities:

• I

2C support

• Three GPIO ports without external logic in addition to

the I

2C port.

Five GPIO ports are available if I

functionality is not used. Every port can be used inputs,

outputs or I/O with external SCI/SMI capabilities.

• Sixteen GPI and sixteen GPO pins using external

buffers (244 buffers for input and 373 latches for output).

Pins 87, 88 and 94 of the VT82C586B are dedicated general

purpose I/O pins that can be used as inputs, outputs or I/O with

external SMI capability. In particular, pins 87 and 88 can be

used to implement a software-implemented I

2C port for system

configuration and general purpose peripheral communication.

Pins 92 and 136 can be configured either as dedicated general

purpose I/O pins or as control signals for external buffers for

implementing up to sixteen GPI and sixteen GPO ports. The

GPI and GPO ports are connected to the SD15-8 and XD7-0.

The configuration is determined in the GPIO4_CFG and

CPIO3_CFG bits of the PIN_CFG register:

GPIO4_CFG: default to 1 to define pin 136 as GPIO4;

set to 0 to redefine the pin as GPO_WE latch enable.

GPIO3_CFG: default to 1 to define pin 92 as GPIO3; set

to 0 to redefine the pin as GPI_RE# buffer enable.

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