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ST72561J4-Auto Datasheet(PDF) 86 Page - STMicroelectronics

Part # ST72561J4-Auto
Description  Clock, reset and supply management
PDF  324 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST72561J4-Auto Datasheet(HTML) 86 Page - STMicroelectronics

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Window watchdog (WWDG)
ST72561-Auto
86/324
Doc ID 12370 Rev 8
Figure 37.
Window watchdog timing diagram
9.6
Low power modes
9.7
Hardware watchdog option
If Hardware Watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the Option Byte description.
T6 bit
Reset
WDGWR
T[5:0] CNT downcounter
time
Refresh Window
Refresh not allowed
(step = 16384/fOSC2)
3Fh
Table 36.
Effect of low power modes on WDG
Mode
Description
SLOW
No effect on Watchdog: the downcounter continues to decrement at normal speed.
WAIT
No effect on Watchdog: the downcounter continues to decrement.
HALT
OIE bit in
MCCSR
register
WDGHALT
bit in Option
Byte
00
No Watchdog reset is generated. The MCU enters Halt mode. The
Watchdog counter is decremented once and then stops counting and is
no longer able to generate a watchdog reset until the MCU receives an
external interrupt or a reset.
If an interrupt is received (refer to interrupt table mapping to see
interrupts which can occur in halt mode), the Watchdog restarts counting
after 256 or 4096 CPU clocks. If a reset is generated, the Watchdog is
disabled (reset state) unless Hardware Watchdog is selected by option
byte. For application recommendations see Section 9.8: Using halt
mode with the WDG (WDGHALT option) below.
0
1
A reset is generated instead of entering halt mode.
ACTIVE
HALT
1x
No reset is generated. The MCU enters Active Halt mode. The
Watchdog counter is not decremented. It stop counting. When the MCU
receives an oscillator interrupt or external interrupt, the Watchdog
restarts counting immediately. When the MCU receives a reset the
Watchdog restarts counting after 256 or 4096 CPU clocks.



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