ST72561J4-Auto datasheet(46/324 Pages) STMICROELECTRONICS

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Supply, reset and clock management

ST72561-Auto

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Doc ID 12370 Rev 8

The LVD function is illustrated in Figure 15.

Provided the minimum VDD value (guaranteed for the oscillator frequency) is above VIT-(LVD),

the MCU can only be in two modes:

●

under full software control

●

in static safe reset

In these conditions, secure operation is always ensured for the application without the need

for external reset hardware.

During a Low Voltage Detector Reset, the RESET pin is held low, thus permitting the MCU

to reset other devices.

Note:

The LVD allows the device to be used without any external RESET circuitry.

The LVD is an optional function which can be selected by option byte.

It is recommended to make sure that the VDD supply voltage rises monotonously when the

device is exiting from Reset, to ensure the application functions properly.

Figure 15.

Low voltage detector vs reset

5.6.2

Auxiliary voltage detector (AVD)

The Voltage Detector function (AVD) is based on an analog comparison between a VIT-(AVD)

and VIT+(AVD) reference value and the VDD main supply. The VIT-(AVD) reference value for

falling voltage is lower than the VIT+(AVD) reference value for rising voltage in order to avoid

parasitic detection (hysteresis).

The output of the AVD comparator is directly readable by the application software through a

real time status bit (AVDF) in the SICSR register. This bit is read only.

Caution:

The AVD function is active only if the LVD is enabled through the option byte.

Monitoring the VDD main supply

If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the

VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles).

In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing

software to shut down safely before the LVD resets the microcontroller (see Figure 16).

The interrupt on the rising edge is used to inform the application that the VDD warning state

is over.

If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay

selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached.

VDD

VIT+(LVD)

RESET

VIT-(LVD)

Vhys

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