ST72561J4-Auto datasheet(42/324 Pages) STMICROELECTRONICS

42 / 324 page

Supply, reset and clock management

ST72561-Auto

42/324

Doc ID 12370 Rev 8

Figure 11.

Clock, reset and supply block diagram

5.4

Multi-oscillator (MO)

The main clock of the ST7 can be generated by two different source types coming from the

multi-oscillator block:

●

an external source

●

a crystal or ceramic resonator oscillator

Each oscillator is optimized for a given frequency range in terms of consumption and is

selectable through the option byte. The associated hardware configuration are shown in

Table 8. Refer to the electrical characteristics section for more details.

Caution:

The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure

Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left

unconnected, the ST7 main oscillator may start and, in this configuration, could generate an

fOSC clock frequency in excess of the allowed maximum (> 16 MHz), putting the ST7 in an

unsafe/undefined state. The product behavior must therefore be considered undefined when

the OSC pins are left unconnected.

External clock source

In external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to

drive the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/ceramic oscillators

This family of oscillators has the advantage of producing a very accurate rate on the main

clock of the ST7. The selection within a list of five oscillators with different frequency ranges

must be done by option byte in order to reduce consumption (refer to Section 22.2.1: Flash

configuration for more details on the frequency ranges). The resonator and the load

capacitors must be placed as close as possible to the oscillator pins in order to minimize

LOW VOLTAGE

DETECTOR

(LVD)

AUXILIARY VOLTAGE

DETECTOR

(AVD)

MULTI-

OSCILLATOR

(MO)

OSC1

RESET

VSS

VDD

RESET SEQUENCE

MANAGER

(RSM)

OSC2

MAIN CLOCK

AVD Interrupt Request

CONTROLLER

PLL

SYSTEM INTEGRITY MANAGEMENT

WATCHDOG

SICSR

TIMER (WDG)

WITH REALTIME

CLOCK (MCC/RTC)

AVD AVD LVD

WDG

fOSC

fOSC2

(option)

fCPU

8-BIT TIMER

/ 8000

ST72561J4-Auto Datasheet(PDF) 42 Page - STMicroelectronics

ST72561J4-Auto Datasheet(HTML) 42 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL