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STM8S003F3 Datasheet(PDF) 42 Page - STMicroelectronics |
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STM8S003F3 Datasheet(HTML) 42 Page - STMicroelectronics |
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42 / 104 page  Option bytes STM8S003F3 STM8S003K3 42/104 DocID018576 Rev 9 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 12. Option bytes Addr. Option name Option byte no. Option bits Factory default setting 7 6 54 32 10 0x4800 Read-out protection (ROP) OPT0 ROP[7:0] 0x00 0x4801 User boot code (UBC) OPT1 UBC[7:0] 0x00 0x4802 NOPT1 NUBC[7:0] 0xFF 0x4803 Alternate function remapping (AFR) OPT2 AFR7 AFR6 AFR5 AFR4 AFR3 AFR2 AFR1 AFR0 0x00 0x4804 NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 0xFF 0x4805 Misc. option OPT3 Reserved HSITRIM LSI _EN IWDG _HW WWDG _HW WWDG _HALT 0x00 0x4806 NOPT3 Reserved NHSI TRIM NLSI _EN NIWDG _HW NWWDG _HW NWWDG _HALT 0xFF 0x4807 Clock option OPT4 Reserved EXT CLK CKAWU SEL PRS C1 PRS C0 0x00 0x4808 NOPT4 Reserved NEXT CLK NCKAW USEL NPR SC1 NPR SC0 0xFF 0x4809 HSE clock startup OPT5 HSECNT[7:0] 0x00 0x480A NOPT5 NHSECNT[7:0] 0xFF Table 13. Option byte description Option byte no. Description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. |
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