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HD64645 Datasheet(PDF) 44 Page - Hitachi Semiconductor |
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HD64645 Datasheet(HTML) 44 Page - Hitachi Semiconductor |
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44 / 50 page  HD64645/64646 44 Memory Interface (V CC = 5.0V ± 10%, GND = 0V, Ta = –20°C to +75°C, unless otherwise noted) Item Symbol Min Typ Max Unit Figure DCLK cycle time t CYCD 100 — — ns 37 DCLK high level width t WDH 30 ——ns DCLK low level width t WDL 30 ——ns DCLK rise time t Dr — — 20 ns DCLK fall time t Df — — 20 ns MCLK delay time t DMD — — 60 ns MCLK rise time t Mr — — 30 ns MCLK fall time t Mf — — 30 ns MA0–MA15 delay time t MAD — — 150 ns MA0–MA15 hold time t MAH 10 ——ns RA0–RA4 delay time t RAD — — 150 ns RA0–RA4 hold time t RAH 10 ——ns DISPTMG delay time t DTD — — 150 ns DISPTMG hold time t DTH 10 ——ns CUDISP delay time t CDD — — 150 ns CUDISP hold time t CDH 10 ——ns CL1 delay time t CL1D — — 150 ns CL1 hold time t CL1H 10 ——ns CL1 rise time t CL1r — — 50 ns CL1 fall time t CL1f — — 50 ns MD0–MD15 setup time t MDS 30 ——ns MD0–MD15 hold time t MDH 15 ——ns |
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