HD64646FS datasheet(39/50 Pages) HITACHI

39 / 50 page

HD64645/64646

Reset

RES pin determines the internal state of LSI counters and the like. This pin does not affect register contents

nor does it basically control output terminals.

Reset is defined as follows (Figure 35):

• At reset: the time when RES goes low

• During reset: the period while RES remains low

• After reset: the period on and after the RES transition from low to high

• Make sure to hold the reset signal low for at least 1 µs

RES pin should be pulled high by users during operation.

Reset State of Pins

RES pin does not basically control output pins, and operates regardless of other input pins.

1. Preserve states before reset

LU0–LU3, LD0–LD3, FLM, CL1, RA0–RA4

2. Fixed at high level

MLCK

3. Preserve states before reset or fixed at low level according to the timing when the reset signal is input

DISPTMG, CUDISP, MA0–MA15

4. Fixed at high or low according to mode

CL2

5. Unaffected

DB0–DB7

Reset State of Registers

RES pin does not affect register contents. Therefore, registers can be read or written even during a reset

state; their contents will be preserved regardless of reset until they are rewritten to.

Notes for HD64645/HD64646

1. The HD64645/HD64646 are CMOS LSIs, and it should be noted that input pins must not be left

disconnected, etc.

2. At power-on, the state of internal registers becomes undefined. The LSI operation is undefined until all

internal registers have been programmed.

HD64646FS Datasheet(PDF) 39 Page - Hitachi Semiconductor