DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL

LVHSTL TRANSLATOR

85222 DATA SHEET

2

REVISION C 5/7/15

Number

Name

Type

Description

1, 2

Q0, nQ0

Output

Differential output pair. LVHSTL interface levels.

3, 4

Q1, nQ1

Output

Differential output pair. LVHSTL interface levels.

5

GND

Power

Power supply ground.

6

CLK1

Input

Pulldown

LVCMOS / LVTTL clock input.

7

CLK0

Input

Pulldown

LVCMOS / LVTTL clock input.

8V

DD

Power

Positive supply pin.

NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

NOTE: Unused output pairs must be terminated. Refer to Application Information section for a schematic layout.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω