IDE Interface

Name

Type

Description

IDE

D 150

IO

12 mA Slew

DRIVE DATA BUS

This is an 8- or 16-bit bi-direction data between the PCI-IDE

chip and the drive The lower 8 bits are used for 8-bit transfers (eg command

Rate Control

registers ECC bytes)

CH0

DA 20

O

12 mA Slew

CHANNEL 0 ADDRESS LINES

This is the 3-bit binary coded address asserted

by the host to access a register or data port in the drive

Rate Control

CH1

DA 20

O

12 mA Slew

CHANNEL 1 ADDRESS LINES

This is the 3-bit binary coded address asserted

by the host to access a register or data port in the drive

Rate Control

IORDY0

I

CHANNEL 0 IO CHANNEL READY

This signal is negated to extend the disk

transfer cycle of any register access (read or write) when the drive is not ready

to respond to a data transfer request

IORDY1

I

CHANNEL 1 IO CHANNEL READY

This signal is negated to extend the disk

transfer cycle of any register access (read or write) when the drive is not ready

to respond to a data transfer request

CH0

IOR

O

12 mA Slew

CHANNEL 0 IO READ

This is the read strobe signal The falling edge of

CH0

IOR

enables data from a register or the data port of the drive onto the

Rate Control

PCI bus

CH0

IOW

O

12 mA Slew

Channel 0 IO Read

This is the write strobe signal The rising edge of CH0

IOW

clocks data from the PCI-IDE chip into the register or the data port of the

Rate Control

drive

CH1

IOR

O

12 mA Slew

CHANNEL 1 IO READ

This is the read strobe signal The falling edge of the

CH1

IOR

enables data from a register or the data port of the drive onto the

Rate Control

PCI bus

CH1

IOW

O

12 mA Slew

CHANNEL 1 IO WRITE

This is the write strobe signal The rising edge of

CH1

IOW

clocks data from the PCI-IDE chip into the register or the data port

Rate Control

of the drive

HDDRST

O

12 mA Slew

DRIVE RESET

This signal from the PCI-IDE chip is triggered by RST

or under

software control which generates IDE reset for a min time of 62 ms

Rate Control

CH0

CS1

O

12 mA Slew

CHANNEL 0 CHIP SELECT 1 AND 3

CH0

CS1

is the chip select signal to

select the Command Block Register CH0

CS3

is the chip select signal to

CH0

CS3

Rate Control

select the Control Block Register

CH1

CS1

O

12 mA Slew

CHANNEL 1 CHIP SELECT 1 AND 3

CH1

CS1

is the chip select signal to

select the Command Block Registers CH1

CS3

is the chip select to select

CH1

CS3

Rate Control

the Control Block Registers

CH0

INT

I

CHANNEL INTERRUPTS

These signals are used to interrupt the host system

CH0

INT is asserted only when the drive(s) on channel 0 has a pending

CH1

INT

interrupt and the host has cleared nIEN in the Device Control Register CH1

INT is asserted only when the drive(s) on channel 1 has a pending interrupt and

the host has cleared nIEN in the Device Control Register

ENABLE

I

CHIP ENABLE PIN

Logic low will disable this chip If this pin is tied to Logic

High or not connected then the chip is enabled

HEADER

I

HEADER PIN

See page 13

IRQ14

OTRI-STATE

8 mA Slew

The output of this pin is equivalent to ISA IRQ14 if HEADER is ‘‘not connected’’

or Logic High However this pin will go to TRI-STATE if HEADER is tied to Logic

Rate Control

low

IRQ15

OTRI-STATE

8 mA Slew

The output of this pin is equivalent to ISA IRQ15 if HEADER is ‘‘Not connected’’

or Logic High However this pin will go to TRI-STATE if HEADER is tied to Logic

Rate Control

low

6