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PC87410 Datasheet(PDF) 11 Page - National Semiconductor (TI) |
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PC87410 Datasheet(HTML) 11 Page - National Semiconductor (TI) |
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11 / 16 page  Relation Table for INTA INTB IRQ1415 with HEADER and channel IO base registers Condition Outcome When chip is disabled (HEADER is ‘‘don’t care’’) and IRQ14 off the setting of channel 01 IO base register setting is IRQ15 off ‘‘don’t care’’ INTA off INTB off16 HEADER is absent (Note 1) chip is enabled and IRQ14 off the setting of channel 01 IO base register setting is IRQ15 off ‘‘don’t care’’ INTA inversion of CH0 INT if CH0 INT is not masked by the bit0 of register 43h Otherwise it is at TRI-STATE INTB inversion of CH1 INT if CH1 INT is not masked by the bit0 of register 47h Otherwise it is at TRI-STATE HEADER is present chip is enabled IRQ14 same value of CH0 INT if CH0 INT is not Channel 0 IO is set at ‘‘primary IDE port’’ masked by the bit0 of register 43h Otherwise it is at TRI-STATE HEADER is present chip is enabled INTA inversion of CH0 INT if CH0 INT is not Channel 0 IO is set at ‘‘other IO port’’ masked by the bit0 of register 43h Otherwise it is at TRI-STATE IRQ14 off HEADER is present chip is enabled IRQ15 same value of CH1 INT if CH1 INT is not Channel 1 IO is set at ‘‘secondary IDE port’’ masked by the bit0 of register 47h Otherwise it is at TRI-STATE HEADER is present chip is enabled INTA inversion of CH1 INT if CH1 INT is not Channel 1 IO is set at ‘‘other IO port’’ masked by the bit0 of register 47h Otherwise it is at TRI-STATE IRQ15 TRI-STATE HEADER is present chip is enabled IRQ14 TRI-STATE Channel 0 is not primary port and IRQ15 TRI-STATE Channel 1 is not secondary port INTA Inversion of ORed value of CH0 INT and CH1 INT if none of the CH0 INT and CH1 INT is masked by the bit0 of their respective registers Otherwise it is at TRI-STATE Note INTB is always at TRI-STATE when HEADER is present Note 1 HEADER absent means Logic Low 11 |
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