AD7985BCPZ datasheet(22/29 Pages) AD

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Data Sheet

AD7985

Rev. C | Page 21 of 28

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when multiple AD7985 devices are

connected to an SPI-compatible digital host. A connection dia-

gram example using two AD7985 devices is shown in Figure 30,

and the corresponding timing is given in Figure 31.

With SDI high, a rising edge on CNV initiates a conversion,

selects CS mode, and forces SDO to high impedance. In this

mode, CNV must be held high during the conversion phase

and the subsequent data readback. (If SDI and CNV are low,

SDO is driven low.) Prior to the minimum conversion time,

SDI can select other SPI devices, such as analog multi-plexers,

but SDI must be returned high before the minimum conversion

time elapses and then held high for the maximum possible

conversion time to avoid the generation of the busy signal

indicator.

When the conversion is complete, the AD7985 enters the

acquisition phase and powers down. Each ADC result can be

read by bringing the SDI input low, which consequently outputs

the MSB onto SDO. The remaining data bits are then clocked by

subsequent SCK falling edges. The data is valid on both SCK

edges. Although the rising edge can be used to capture the data,

a digital host using the SCK falling edge allows a faster reading

rate, provided that it has an acceptable hold time. After the 16th

SCK falling edge, SDO returns to high impedance and another

AD7985 can be read.

AD7985

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

CS1

CS2

AD7985

SDI

SDO

CNV

SCK

Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram

tCONV

AQUISITION

tSCKH

tSCKL

tSCK

CONVERSION

SCK

CNV

tSSDICNV

tHSDICNV

SDO

D15

D13

D14

D15

D14

tHSDO

tDSDO

tEN

tDIS

SDI (CS1)

SDI (CS2)

tQUIET

tACQ

tCYC

Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing

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