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AD7985BCPZ Datasheet(PDF) 23 Page - Analog Devices

Part # AD7985BCPZ
Description  16-Bit, 2.5 MSPS, PulSAR 15.5 mW ADC in LFCSP
PDF  29 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7985BCPZ Datasheet(HTML) 23 Page - Analog Devices

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AD7985
Data Sheet
Rev. C | Page 22 of 28
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7985 is connected
to an SPI-compatible digital host with an interrupt input and
when it is desired to keep CNV, which samples the analog input,
independent of the signal that selects the data reading. This
independence is particularly important in applications where
low jitter on CNV is desired. This mode is available only in normal
conversion mode (TURBO is low). The connection diagram is
shown in Figure 32, and the corresponding timing is given in
Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.)
Prior to the minimum conversion time, SDI can select other SPI
devices, such as analog multiplexers, but SDI must be returned
low before the minimum conversion time elapses and then held
low for the maximum possible conversion time to guarantee the
generation of the busy signal indicator.
When the conversion is complete, SDO goes from high imped-
ance to low impedance. With a pull-up on the SDO line, this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7985 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
capture the data, a digital host using the SCK falling edge allows
a faster reading rate, provided that it has an accept-able hold
time. After the optional 17th SCK falling edge or when SDI goes
high (whichever occurs first), SDO returns to high impedance.
AD7985
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
IRQ
VIO
47kΩ
CS1
TURBO
Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram
(I/O QUIET
TIME)
SDO
D15
D14
D1
D0
tDIS
tQUIET
SCK
1
2
3
15
16
17
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
TURBO = 0
Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing



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